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參數(shù)資料
| 型號： | AD1955 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Performance Multibit DAC with SACD Playback |
| 中文描述： | 高性能多位DAC，具有SACD的播放 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大小： | 259K |
| 代理商： | AD1955 |
AD1955
Rev. PrF
-5-
PRELIMINARY TECHNICAL DATA
PIN FUNCTION DESCRIPTIONS
Pin
I/O
1
2
Input
Pin Name
DVDD
EF_WCLK/LRCLK
Description
Digital Power Supply Connected to Digital 5V supply.
Word Clock in External Filter mode.
Left/Right Clock input for input data in PCM mode.
Bit Clock input in External Filter mode. Bit Clock input for input data in PCM mode.
EF_LDATA/SDATA 8fs or 4fs L-ch Data input in External filter mode. Data should be MSB first two’s
complement format. In the PCM mode, serial input, MSB first, containing two
channels(left and right) of 16 to 24bit two’s complement 1fs data.
EF_RDATA
8fs or 4fs R-ch Data input in External filter mode. Data should be MSB first two’s
complement format. Not used in PCM mode
DSD_SCLK
Shift clock input for DSD data. This clock should be 64x44.1kHz, 2.8224MHz or
128x44.1kHz, 5.6448MHz in normal mode or 128x44.1kHz, 5.6448MHz or
256x44.1kHz, 11.2896MHz in phase mode.
DSD_LDATA
DSD Left channel data input
DSD_RDATA
DSD Right channel data input
DSD_PHASE
DSD phase reference signal. This clock should be 64x44.1kHz, 2.8224MHz. If not
used this pin should be connected Low.
AGND
Analog Ground
IOUTR+
Right Channel Positive analog output.
IOUTR-
Right Channel Negative analog output.
FILTR
Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage
reference with parallel 10uF and 0.1uF capacitors to AGND
IREF
Connection point for external bias resistor.
AVDD
Analog power supply Connected to Analog 5V supply
FILTB
Filter Capacitor Connection with parallel 10uF and 0.1uF capacitors to AGND
IOUTL-
Left Channel Negative analog output.
IOUTL+
Left Channel Positive analog output.
AGND
Analog Ground
ZEROR
Right Channel Zero Flag Output. This pin goes high when the right channel has no
signal input or the DSD mute pattern is detected.
ZEROL
Left Channel Zero Flag Output. This pin goes high when the left channel has no signal
input or the DSD mute pattern is detected.
MUTE
Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal
operation.
PD/RST
Power down/Reset. The AD1955 is placed in a reset state and the digital circuitry is
powered down when this pin is held LO. The AD1955 is reset on the rising edge of
this signal. The serial control port registers are reset to the default values. Connect HI
for normal operation.
CDATA
Serial control input, MSB first, containing 16 bits of unsigned data. Used for
specifying control information and channel-specific attenuation.
CLATCH
Latch Input for control data.
CCLK
Control Clock input for control data. Control input data must be valid on the rising
edge of CCLK. CCLK may be continuous or gated.
MCLK
Master Clock Input. Connect to an external clock source.
DGND
Digital Ground
3
4
Input
Input
EF_BCLK/BCLK
5
Input
6
I/O
7
8
9
Input
Input
I/O
10
11
12
13
Output
Output
Output
14
15
16
17
18
19
20
Output
Output
Output
Output
21
Output
22
Input
23
Input
24
Input
25
26
Input
Input
27
28
Input
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