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參數(shù)資料
| 型號(hào)： | AD1953 |
| 廠商： | Analog Devices, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點(diǎn) DSP |
| 文件頁(yè)數(shù)： | 22/36頁(yè) |
| 文件大?。?/td> | 750K |
| 代理商： | AD1953 |
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REV. 0
AD1953
–22–
Table IV. Control Register 1 READ Definition
Register Bits
Function
1
DSP Core Shutdown Complete
1 = Shutdown Complete
0 = Not Shut Down
Safe Memory Load Complete
1 = Complete (Note: Cleared after Read)
0 = Not Complete
0
Bit 0 is asserted when all requested safeload registers have been
transferred to the parameter RAM. It is cleared after the read
operation is complete.
Bit 1 is asserted after the requested shutdown of the DSP is
completed. When this bit is set, the user is free to write or read
any RAM location without causing an audio pop or click.
Table V. Control Register 2 WRITE Definition
Register Bits
Function
9
Volume Ramp Speed
1 = 160 ms Full-Ramp Time
0 = 20 ms Full-Ramp Time
Serial Port Output Enable
1 = Enabled
0 = Disabled
Serial Port Input Select
00 = IN0
01 = IN1
10 = IN2
11 = NA
MCLK Input Select
00 = MCLK0
01 = MCLK1
10 = MCLK2
11 = NA
Reserved
MCLK In Frequency Select
0 = 512
×
f
S
1 = 256
×
f
S
MCLK Out Frequency Select
00 Disabled
01 512
×
f
S
10 256
×
f
S
11 MCLKO = MCLK_In (Feedthrough)
8
7:6
5:4
3
2
1:0
Control Register 2
Table V documents the contents of Control Register 2. Bits
<1:0> set the frequency of the MCLKO pin. If these bits are set
to 00, the MCLKO pin is disabled (default). When set to 01,
the MCLKO pin is set to 512
×
f
S
, which is the same as the
internal master clock used by the DSP core. When set to 10,
this pin is set to 256
×
f
S
, derived by dividing the internal DSP
clock by 2. In this mode, the output 256
×
f
S
clock will be inverted
with respect to the input 256
×
f
S
clock. This is not the case with
the feedthrough mode. When set to 11, the MCLKO pin mirrors
the selected MCLK input pin (it’s the output of the MCLK
MUX selector). Note that the internal DSP master clock may
either be the same as the selected MCLK pin (when MCLK
frequency select is set to 512
×
f
S
mode) or may be derived from
the MCLK pin using internal clock doubler (when MCLK fre-
quency select is set to 256
×
f
S
)
.
Bit <2> selects one of two possible MCLK input frequencies. When
set to 0 (default), the MCLK frequency is set to 512
×
f
S
. In this mode,
the internal DSP clock and the external MCLK are at the same
frequency. When set to 1, the MCLK frequency is set to 256
×
f
S
, and
an internal clock doubler is used to generate the DSP clock.
Bits <5:4> select one of three clock input sources using an inter-
nal MUX. To avoid click and pop noises when switching MCLK
sources, it is recommended that the user put the DSP core in
shutdown before switching MCLK sources.
Bits <7:6> select one of three serial input sources using an inter-
nal MUX. Each source selection includes a separate SDATA,
LRCLK, and BCLK input. To avoid click and pop noises when
switching serial sources, it is recommended that the user put the
DSP core in shutdown before writing to these bits.
Bit <8> is used to enable the three serial output pins. These pins
are connected to the output of the serial input MUX, which is set
by Bits <7:6>. The default is 0 (disabled).
Bit <9> changes the default setting of the volume ramp speed.
When set to 0, it will take 1024 LRCLK periods to go from full
volume (6 dB) to infinite attention. When set to 1, the same
operation will take 8192 LRCLK periods.
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