- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373862 > AD1895YRS (ANALOG DEVICES INC) 192 kHz Stereo Asynchronous Sample Rate Converter PDF資料下載
參數(shù)資料
| 型號(hào)： | AD1895YRS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 192 kHz Stereo Asynchronous Sample Rate Converter |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大小： | 816K |
| 代理商： | AD1895YRS |
REV. A
AD1895
–17–
FREQUENCY DOMAIN OF SAMPLES AT f
S_IN
FREQUENCY DOMAIN OF THE INTERPOLATION
FREQUENCY DOMAIN OF f
S_OUT
RESAMPLING
FREQUENCY DOMAIN AFTER
RESAMPLING
IN
OUT
f
S_IN
f
S_OUT
INTERPOLATE
BY N
LOW-PASS
FILTER
ZERO-ORDER
HOLD
f
S_IN
2
20
f
S_IN
2
20
f
S_IN
2
20
f
S_IN
SIN(X)/X OF ZERO-ORDER HOLD
Figure 6. Frequency Domain of the Interpolation and
Resampling
HARDWARE MODEL
The output rate of the low-pass filter of Figure 5 would be the
interpolation
rate, 2
20
×
192000 kHz = 201.3 GHz. Sampling at
a rate of 201.3 GHz is clearly impractical, not to mention the
number of taps required to calculate each interpolated sample.
However, since interpolation by 2
20
involves zero-stuffing 2
20
–1
samples between each f
S_IN
sample, most of the multiplies in
the low-pass FIR filter are by zero. A further reduction can be
realized by the fact that since only one interpolated sample is
taken at the output at the f
S_OUT
rate, only one convolution
needs to be performed per f
S_OUT
period instead of 2
20
convo-
lutions. A 64-tap FIR filter for each f
S_OUT
sample is sufficient
to suppress the images caused by the interpolation.
The difficulty with the above approach is that the correct inter-
polated sample needs to be selected upon the arrival of f
S_OUT
.
Since there are 2
20
possible convolutions per f
S_OUT
period, the
arrival of the f
S_OUT
clock must be measured with an accuracy
of 1/201.3 GHz = 4.96 ps. Measuring the f
S_OUT
period with a
clock of 201.3 GHz frequency is clearly impossible; instead,
several coarse measurements of the f
S_OUT
clock period are made
and averaged over time.
Another difficulty with the above approach is the number of
coefficients required. Since there are 2
20
possible convolutions
with a 64-tap FIR filter, there need to be 2
20
polyphase coeffi-
cients for each tap, which requires a total of 2
26
coefficients. To
reduce the number of coefficients in ROM, the AD1895 stores a
small subset of coefficients and performs a high-order interpola-
tion between the stored coefficients. So far the above approach
works for the case of f
S_OUT
> f
S_IN
. However, in the case when
the output sample rate, f
S_OUT
, is less than the input sample
rate, f
S_IN
, the ROM starting address, input data and the length
of the convolution must be scaled. As the input sample rate
rises over the output sample rate, the antialiasing filter’s cutoff
frequency has to be lowered because the Nyquist frequency of
the output samples is less than the Nyquist frequency of the
input samples. To move the cutoff frequency of the antialiasing
filter, the coefficients are dynamically altered and the length
of the convolution is increased by a factor of (f
S_IN
/f
S_OUT
).
This technique is supported by the Fourier transform property
that if f(t) is F(
ω
), then f(k
×
t) is F(
ω
/k). Thus, the range of
decimation is simply limited by the size of the RAM.
THE SAMPLE RATE CONVERTER ARCHITECTURE
The architecture of the sample rate converter is shown in Figure
7. The sample rate converter’s FIFO block adjusts the left and
right input samples and stores them for the FIR filter’s convolu-
tion cycle. The f
S_IN
counter provides the write address to the
FIFO block and the ramp input to the digital servo loop. The
ROM stores the coefficients for the FIR filter convolution and
performs a high-order interpolation between the stored coeffi-
cients. The sample rate ratio block measures the sample rate for
dynamically altering the ROM coefficients and scaling of the
FIR filter length as well as the input data. The digital servo loop
automatically tracks the f
S_IN
and f
S_OUT
sample rates and pro-
vides the RAM and ROM start addresses for the start of the FIR
filter convolution.
RIGHT DATA IN
LEFT DATA IN
FIFO
ROM A
ROM B
ROM C
ROM D
HIGH
ORDER
INTERP
DIGITAL
SERVO LOOP
FIR FILTER
SAMPLE RATE
RATIO
f
COUNTER
SAMPLE RATE RATIO
EXTERNAL
RATIO
f
S_IN
f
S_OUT
L/R DATA OUT
Figure 7. Architecture of the Sample Rate Converter
The FIFO receives the left and right input data and adjusts the
amplitude of the data for both the soft muting of the sample rate
converter and the scaling of the input data by the sample rate
ratio before storing the samples in the RAM. The input data
is scaled by the sample rate ratio because as the FIR filter length
of the convolution increases, so does the amplitude of the convo-
lution output. To keep the output of the FIR filter from saturating,
the input data is scaled down by multiplying it by (f
S_OUT
/f
S_IN
)
when f
S_OUT
< f
S_IN
. The FIFO also scales the input data for
muting and unmuting of the AD1895.
The RAM in the FIFO is 512 words deep for both left and right
channels. A small offset of 16 is added to the write address
provided by the f
S_IN
counter to prevent the RAM read pointer
from ever overlapping the write address. The maximum deci-
mation rate can be calculated from the RAM word depth as
(512–16)/64 taps = 7.75 and a small offset.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1895AYRS | 10-Bit, Complete, 40 MSPS, dual Transmit D/A Converter; Package: Evaluation Boards; No of Pins: -; Temperature Range: Industrial |
| AD1895AYRSRL | 192 kHz Stereo Asynchronous Sample Rate Converter |
| AD1953 | 16-bit fixed point DSP with Flash |
| AD1953YST | 16-bit fixed point DSP with Flash |
| AD1953YSTRL | 16-bit fixed point DSP with Flash |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1895YRSRL | 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC S - Bulk |
| AD1896 | 制造商:AD 制造商全稱:Analog Devices 功能描述:192 kHz Stereo Asynchronous Sample Rate Converter |
| AD1896AYRS | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC SAMPLE RATE CONV - Bulk 制造商:Analog Devices 功能描述:IC STEREO ASR CONVERTER |
| AD1896AYRSRL | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin SSOP T/R |
| AD1896AYRSZ | 功能描述:IC CONV SAMPLE RATE ASYNC 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。