參數(shù)資料
型號(hào)： AD1893
廠(chǎng)商： Analog Devices, Inc.
英文描述： Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter(低成本采樣端口16位立體聲異步采樣率轉(zhuǎn)換器)
中文描述： 低成本SamplePort 16位立體聲異步采樣率轉(zhuǎn)換器（低成本采樣端口16位立體聲異步采樣率轉(zhuǎn)換器）
文件頁(yè)數(shù)： 10/20頁(yè)
文件大?。?/td> 338K
代理商： AD1893
AD1893
–10–
REV. 0
sample clock events. Figure 5 shows the desired filter group
delay as a function of the relative time difference between the
current output sample clock and the last input sample clock. If
an output sample is requested late in the input sample period,
then a short filter delay is required, and if an output sample is
requested early in the input sample period, then a long filter
delay is required. This nonintuitive result arises from the fact
that FIR filters always produce some delay, so that selecting a
filter with shorter delay moves the interpolated sample closer to
the newest input sample.
Figure 5. Input and Output Clock Event Relationship
A short delay corresponds to a large offset into the dense FIR
filter coefficient array, and a long delay corresponds to a small
offset. Note that because the output sample clock can arrive at
any arbitrary time with respect to the input sample clock, the
selection of a polyphase filter with which to convolve the input
sequence occurs on every output sample clock event. Occasion-
ally the FIFO which holds the input sequence in the FIR con-
volver is either not incremented, or incremented by two between
output sample clocks (see periods A and B in Figure 5); this
happens more often when the input and output sample clock
frequencies are dissimilar than when they are close together.
However, in this situation, an appropriate polyphase filter is
selected to process the input signal, and thus an accurate output
sample is computed. Input and output samples are not skipped
or repeated (unless the input FIFO underflows or overflows), as
is the case in some other sample rate converter implementations.
To obtain an accurate conversion, a large number of polyphase
filters are needed. The AD1893 SamplePort uses the equivalent
of 65,536 polyphase filters to achieve its high quality distortion
and dynamic range specifications.
Sample Clock Tracking
It should be clear that, in either model, the correct computation
of the ratio between the input sample rate (as determined from
the left/
right
input clock, L
R
_I) and the output sample rate (as
determined from the left/
right
output clock, L
R
_O) is critical to
the quality of the output data stream. It is straightforward to
compute this ratio if the sample rates are fixed and synchronous;
the challenge is to accurately track dynamically varying and
asynchronous sample rates, as well as to account for jitter.
The AD1893 SamplePort solves this problem by embedding the
ratio computation circuit within a digital servo control loop, as
shown in Figure 6. This control loop includes special provisions
to allow for the accurate tracking of dynamically changing
sample rates. The outputs of the control loop are the starting
read addresses for the input data FIFO and the filter coefficient
ROM. These start addresses are used by the FIFO and ROM
address generators, as shown in Figure 6.
The input data FIFO write address is generated by a counter
which is clocked by the input sample clock (i.e., L
R
_I). It is very
important that the FIFO read address and the FIFO write
address do not cross, as this means that the FIFO has either
underflowed or overflowed. This consideration affects the
choice of settling time of the control loop. When a step change
in the sample rate occurs, the relative positions of the read and
write addresses will change while the loop is settling. A fast
settling loop will act to keep the FIFO read and write addresses
separated better than a slow settling loop. The AD1893 includes
a user selectable pin (SETLSLW) to set the loop settling time
that essentially changes the coefficients of the digital servo
control loop filter. The state of the SETLSLW pin can be
changed on-the-fly but is normally set and forgotten.
Figure 6. AD1893 Functional Block Diagram
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1893JN 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PDIP W 制造商:Rochester Electronics LLC 功能描述:LOW COST ASRC PDIP 28-PIN - Bulk
AD1893JNZ 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PDIP W
AD1893JST 制造商:Analog Devices 功能描述:Sample Rate Converter 44-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:LOW COST ASRC 44-PIN TQFP - Tape and Reel 制造商:Analog Devices 功能描述:IC ASR CONVERTER 16 BIT
AD1893JSTZ 功能描述:IC SAMPLE-RATE CONV 16BIT 44TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 線(xiàn)性 - 音頻處理 系列:SamplePort™ 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類(lèi)型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱(chēng):497-11050-6
AD1893JSTZRL 功能描述:IC SAMPLE-RATE CONV 16BIT 44TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 線(xiàn)性 - 音頻處理 系列:SamplePort™ 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類(lèi)型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱(chēng):497-11050-6
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