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參數(shù)資料
| 型號(hào)： | AD1892JR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Integrated Digital Receiver/Rate Converter |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 231K |
| 代理商： | AD1892JR |
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltage
Ambient Temperature
Output Sample Frequency (F
SOUT
)
MCLK
Input Word Width
Load Capacitance
All minimums and maximums tested except as noted.
+5.0
25
48.8
25
20
100
V
°
C
kHz
MHz (512
×
F
SOUT
)
Bits
pF
PERFORMANCE
1
Min
120
Typ
Max
Units
dB
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
Total Harmonic Distortion + Noise
(20 Hz to 20 kHz, Full-Scale Input)
(1 kHz Full-Scale Input)
(10 kHz Full-Scale Input)
Interchannel Phase Deviation
–103
–113
–107
0
dB
dB
dB
Degrees
DIGITAL I/O
1
Min
2.4
Typ
Max
Units
V
V
μ
A
μ
A
V
V
pF
V
IH
V
IL
I
IH
@ V
IH
= +5.0 V
I
IL
@ V
IL
= 0 V
V
OH
@ I
OH
= –0.5 mA
V
OL
@ I
OL
= 0.5 mA
Input Capacitance
1
0.8
10
10
DVDD – (0.5)
0.5
15
DIGITAL TIMING
1
Min
40
Typ
Max
60
25
Units
%
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
MCP
F
MCLK
t
PDRP
t
BDM
t
LDM
t
DDP
t
DDS
t
DDH
t
SSU
t
CCH
t
CCL
t
CCP
t
CSU
t
CHD
t
COH
t
SFPW
t
SFSU
t
CSPW
t
QDH
t
CLH
t
CLK
t
RS
MCLK Duty Cycle
1
MCLK Frequency (1/t
MCP
)
1
PD/RST
LO Pulsewidth
BCLK Propagation Delay from MCLK (to Falling Edge)
L
R
CLK Propagation Delay from MCLK
Data Propagation Delay from MCLK
Data Output Setup to BCLK
Data Output Hold from BCLK
SYNC Falling Setup to MCLK Rising
CCLK HI Pulsewidth
CCLK LO Pulsewidth
CCLK Period
SDI Setup
SDI Hold
SDO Propagation Delay from CCLK
SFCLK HI Pulsewidth
1
U/CBIT, INT, ERROR Setup to SFCLK
CSCLK HI Pulsewidth
1
QDFS HI Pulsewidth
1
CS HI Pulsewidth
CS Falling Edge to CCLK Rising
PD/RST Rising to MCLK Rising Edge (Only Required
for Synchronizing Multiple Parts)
10
×
MCLK Period
30
30
30
1/2 BCLK Period
1/2 BCLK Period
5
20
20
8
×
MCLK Period
15
10
30
100
100
100
1000
10
×
MCLK Period
3
×
MCLK Period
5
ns
DIGITAL RS-422 RECEIVERS
(RXP, RXN Pins Only)
Min
Typ
20
Max
Units
k
mV p-p
mV
Input Resistance
Min Differential AES/EBU or S/PDIF Input
Input Hysteresis
200
20
AD1892–SPECIFICATIONS
REV. 0
–2–
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