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參數(shù)資料
| 型號(hào)： | AD1891JN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SamplePort Stereo Asynchronous Sample Rate Converters |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 416K |
| 代理商： | AD1891JN |
AD1890/AD1891
–6–
REV. 0
Output Control Signals
Pin Name
Number
I/O
Description
BK POL_O
19
I
Bit clock polarity. LO: Normal mode. Output data is valid on rising edges of BCLK _O, changed
on falling. HI: Inverted mode. Output data is valid on falling edges of BCLK _O, changed on rising.
T RGLR_O
18
I
T rigger on L
R
_O. HI: Changes in L
R
_O indicate beginning
1
of valid output data. LO: Rising
edge of WCLK _O indicates beginning of valid output data.
MSBDLY_O 17
I
MSB delay. HI: Output data is delayed one BCLK _O after either L
R
_O (T RGLR_O = HI) or
WCLK _O (T RGLR_O = LO) indicates the beginning of valid output data. Included for I
2
S data
format compatibility. LO: No delay.
Miscellaneous
Pin Name
Number
I/O
Description
GPDLYS
1
I
AD1890 ONLY: Group delay—short. HI: Short group delay mode (
≈
700
μ
s). More sensitive to
changes in sample rates (L
R
clocks). LO: Long group delay mode (
≈
3 ms). More tolerant of
sample rate changes. T his signal may be asynchronous with respect to MCLK , and dynamically
changed, but is normally pulled up or pulled down on a static basis. AD1891: Short group delay
mode only; this pin is a N/C.
MCLK
2
I
Master clock input. Nominally 16 MHz for sampling frequencies (F
S
, word rates) from 8 kHz to
56 kHz. Exact frequency is not critical, and does not need to be synchronized to any other clock
or possess low jitter.
RESET
13
I
Active LO reset. Set HI for normal chip operation.
MUT E_O
16
O
Mute output. HI indicates that data is not currently valid due to read and write FIFO memory
pointer overlap. LO indicates normal operation.
MUT E_I
15
I
Mute input. HI mutes the serial output to zeros (midscale). Normally connected to MUT E_O.
Reset LO for normal operation.
SET LSLW
28
I
Settle slowly to changes in sample rates. HI: Slow-settling mode (
≈
800 ms). Less sensitive to
sample clock jitter. LO: Fast-settling mode (
≈
200 ms). Some narrow-band noise modulation may
result from jitter on L
R
clocks. T his signal may be asynchronous with respect to MCLK , and
dynamically changed, but is normally pulled up or pulled down on a static basis.
N/C
9, 20
No connect. Reserved. Do not connect.
Power Supply Connections
Pin Name
Number
I/O
Description
V
DD
7, 22
I
Positive digital voltage supply.
GND
8, 14, 21, 27
I
Digital ground. Pins 14 and 27 need not be decoupled.
NOT E
1
T he beginning of valid data will be delayed by one BCLK _O if MSBDEL _O is selected (Hl).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1891JP | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PLCC 制造商:Rochester Electronics LLC 功能描述:IC, 16-BIT CONVERTER IC - Bulk |
| AD1892 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Digital Receiver/Rate Converter |
| AD1892JR | 制造商:Analog Devices 功能描述:Receiver/Rate Converter 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:INTEGRATED DIG.RECEIVER/RATE CONVERTER - Bulk |
| AD1892JRRL | 制造商:Analog Devices 功能描述:Receiver/Rate Converter 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:INTEGRATED DIG.RECEIVER/RATE CONVERTER - Bulk |
| AD1892JRZ | 制造商:Analog Devices 功能描述:Receiver/Rate Converter 28-Pin SOIC W |
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