參數(shù)資料
型號(hào): AD1888JSTZ-REEL
廠商: ANALOG DEVICES INC
元件分類: 消費(fèi)家電
英文描述: CONNECTOR COAXIAL BNC
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: LEAD FREE, MS-026BBC, LQFP-48
文件頁(yè)數(shù): 26/32頁(yè)
文件大?。?/td> 312K
代理商: AD1888JSTZ-REEL
REV. 0
–26–
AD1888
MBG[1:0]
MIC Boost Gain Select Register.
These two bits allow changing the MIC preamp gain from the nominal 20 dB gain. Both MIC1/MIC2 and MIC2
preamps will be set to the same selected gain.
Note that this gain takes effect only while Bit D6 (M20) on the MIC volume register (0Eh) is set to 1; otherwise, the
MIC boost block has a gain of 0 dB.
00 = 20 dB gain (reset default)
01 = 10 dB gain
10 = 30 dB gain
11 = reserved
VREFD
V
REFOUT
Disable. Disables V
REFOUT
, placing it into High-Z out mode.
Note that this bit overrides the VREFH bit selection (see below).
0 = V
REFOUT
pin is driven by the internal reference (reset default).
1 = V
REFOUT
pin is placed into High-Z out mode.
V
REFOUT
High. Changes V
REFOUT
from 2.25 V to 3.70 V for PC2001 compliant MIC bias applications.
0 = V
REFOUT
pin is set to 2.25 V output (reset default).
1 = V
REFOUT
pin is set to 3.70 V output.
Sample Rate Unlock. Controls DAC sample rate locking.
0 = All DAC sample rates are locked to the front sample rate (reset default).
1 = DAC sample rates can be set independently for front, surround, and LFE.
VREFH
SRU
LOSEL
LINE_OUT Amplifiers Input Select. This bit allows the LINE_OUT output amplifiers to be driven by the mixer
or the surround DACs. The main purpose for this is to allow swapping of the front and surround channels to make
better use of the SURR/HP_OUT output amplifiers. This bit should normally be used in tandem with the HPSEL
bit (see below).
0 = LINE_OUT amplifiers are driven by the mixer outputs (reset default).
1 = LINE_OUT amplifiers are driven by the surround DAC outputs.
SPRD
SPREAD Enable. This bit enables spreading of 2-channel media to all six output channels. This function is imple-
mented in the analog section by using the output selector controls line for the center/LFE, surround, and Line_out
output channels. Note that the Jack Sense pins can also be set up to control (gate) this function, depending on the
JSSPRD bit (see Register 72h).
0 = No spreading occurs unless activated by the Jack Senses and JSSPRD bits (reset default).
1 = The SPRD selector drives the center and LFE outputs from the MONO_OUT, the HPSEL selector drives the
SURR/HP_OUT outputs from the mixer outputs, and the LOSEL selector drives the LINE_OUT outputs also
from the mixer outputs.
Note that the SPRD bit overrides the current output selector control lines set up by bits LOSEL and HPSEL as
follows: LOSEL = 0 and HPSEL = 1.
Miscellaneous Control Bit Register (Index 76h)
Reg
No. Name D15
De-
fault
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
76h Misc
DACZ AC97NC MSPLT LODIS CLDIS HPSEL DMIX1 DMIX0 SPRD X
LOSEL SRU VREFH VREFD MBG1MBG0 0000h
Control
Bits
相關(guān)PDF資料
PDF描述
AD1890JN SamplePort Stereo Asynchronous Sample Rate Converters
AD1891JN SamplePort Stereo Asynchronous Sample Rate Converters
AD1891JP SamplePort Stereo Asynchronous Sample Rate Converters
AD1890JP SamplePort Stereo Asynchronous Sample Rate Converters
AD1890 SamplePort Stereo Asynchronous Sample Rate Converters
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1889JS 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD1890 制造商:AD 制造商全稱:Analog Devices 功能描述:SamplePort Stereo Asynchronous Sample Rate Converters
AD1890JN 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PDIP W 制造商:Rochester Electronics LLC 功能描述:IC, 20-BIT CONVERTER IC - Bulk
AD1890JNZ 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PDIP W
AD1890JP 制造商:Rochester Electronics LLC 功能描述:IC, 20-BIT CONVERTER IC - Bulk 制造商:Analog Devices 功能描述:IC 20-BIT CONVERTER