
REV. 0
–4–
AD1887–SPECIFICATIONS
CLOCK SPECIFICATIONS
*
Parameter
Min
Typ
Max
Unit
Input Clock Frequency
Recommended Clock Duty Cycle
24.576
50
MHz
%
40
60
POWER-DOWN STATES
Parameter
Set Bits
DV
DD
Typ
15.82
15.08
3.79
3.85
17.65
15.70
15.07
3.80
3.85
0.06
0.06
17.66
AV
DD
Typ
30.0
26.3
19.9
18.1
17.4
11.1
8.3
2.1
18.1
18.1
0
26.1
Unit
ADC
DAC
ADC + DAC
ADC + DAC + Mixer (Analog CD On)
Mixer
ADC + Mixer
DAC + Mixer
ADC + DAC + Mixer
Analog CD Only (AC-Link On)
Analog CD Only (AC-Link Off)
Standby
Headphone Standby
PR0
PR1
PR1, PR0
LPMIX, PR1, PR0
PR2
PR2, PR0
PR2, PR1
PR2, PR1, PR0
LPMIX, PR5, PR1, PR0
LPMIX, PR1, PR0, PR4, PR5
PR5, PR4, PR3, PR2, PR1, PR0
PR6
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
*
Guaranteed but not tested.
Specifications subject to change without notice.
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
Symbol
Min
Typ
Max
Unit
μ
s
ns
μ
s
μ
s
ns
MHz
ns
ps
ns
ns
kHz
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
ns
ns
ns
ns
ns
RESET Active Low Pulsewidth
RESET Inactive to BIT_CLK Startup Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Startup Delay
BIT_CLK Frequency
BIT_CLK Period
BIT_CLK Output Jitter
*
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)
Rising Edge of RESET to HI-Z Delay
Propagation Delay
RESET Rise Time
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
t
RST_LOW
t
RST2CLK
t
SYNC_HIGH
t
SYNC_LOW
t
SYNC2CLK
1.0
162.8
1.3
19.5
162.8
12.288
81.4
t
CLK_PERIOD
750
48.84
48.84
t
CLK_HIGH
t
CLK_LOW
32.56
32.56
42
38
48.0
20.8
2.5
t
SYNC_PERIOD
t
SETUP
t
HOLD
t
RISECLK
t
FALLCLK
t
RISESYNC
t
FALLSYNC
t
RISEDIN
t
FALLDIN
t
RISEDOUT
t
FALLDOUT
t
S2_PDOWN
t
SETUP2RST
t
OFF
5
5
2
2
2
2
2
2
2
2
0
15
4
4
4
4
4
4
4
4
6
6
6
6
6
6
6
6
1.0
25
15
50
15
*
Output jitter is directly dependent on crystal input jitter.
Specifications subject to change without notice.