參數(shù)資料
型號: AD1885JST
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: AC’97 SoundMAX Codec
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: PLASTIC, LQFP-48
文件頁數(shù): 19/27頁
文件大?。?/td> 291K
代理商: AD1885JST
AD1885
–19–
REV. 0
Extended Audio Status and Control Register (Index 2Ah)
u
u
u
N m
u
u
Re
R g
e
m
a
N
1
D 5
1
D 4
1
D 3
1
D 2
D 1
1
D 0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
u
a
f
D
2A
2 h
l
C
l
/
S
o
o
i
d
u
A
d
e
d
n
e
x
E
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VR
V A
h
0
0
0
0
Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio
features.
VRA
Variable Rate Audio. VRA = 1 enables support for Variable Rate Audio mode (sample rate control registers and
SLOTREQ signaling).
PCM DAC Rate Register (Index 2Ch)
u
u
u
N m
u
u
Re
R g
e
m
a
N
1
D 5
1
D 4
1
D 3
1
D 2
D 1
1
D 0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
u
a
f
D
)
h
A
7
(
h
C
2
e
a
R
C
A
D
M
C
P
5
1
R
S
4
1
R
S
3
1
R
S
2
1
R
S
1
1
R
S
0
1
R
S
R
S 9
R
S 8
R
S 7
R
S 6
R
S 5
R
S 4
R
S 3
R
S 2
R
S 1
R
S 0
h
0
8
B
B
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample
rates are reset to 48 kHz.
SR[15:0]
Writing to this register allows programming of the sampling frequency from 7040 Hz (1B80h) to 48 kHz (BB80h)
in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (BB80h) causes the
codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back
when read, otherwise the closest rate supported is returned.
PCM ADC Rate Register (Index 32h)
u
u
u
u
N m
u
e
R g
e
e
m
a
N
1
D1
D 5
1
D1
D 4
1
D1
D 3
1
D1
D 2
D1
D 1
1
D1
D 0
D9
D
D8
D
D7
D
D6
D
D5
D
D4
D
D3
D
D2
D
D1
D
D0
D
t
u
u
a
f
D
)
h
8
7
(
h
2
3
e
a
R
C
D
A
M
C
P
5
1
R
S
4
1
R
S
3
1
R
S
2
1
R
S
1
1
R
S
0
1
R
S
R
S 9
R
S 8
R
S 7
R
S 6
R
S 5
R
S 4
R
S 3
R
S 2
R
S 1
R
S 0
h
0
8
B
B
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample
rates are reset to 48 kHz.
SR[15:0]
Writing to this register allows programming of the sampling frequency from 7040 Hz (1B80h) to 48 kHz (BB80h)
in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (BB80h) causes the
codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back
when read; otherwise, the closest rate supported is returned.
Jack Sense/Audio Interrupt/Status Register (Index 72h)
u
u
u
u
N m
u
e
R g
e
m
a
N
1
D 5
1
D 4
1
D 3
1
D 2
D 1
1
1
D 0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
u
a
f
D
2
7 h
o
i
s
d
u
u
t
A
t
/
s
/
p
n
e
u
S
r
k
c
e
n
a
J
I
a
S
r
/
T
U
T
O
C
_
N
1
S
U
F
J
_
0
S
J
OU
O T
U
P
JS
J 1
S
I
D
U
P
JS
J 0
S
I
D
JS
J 1
OE
O
_
S
J 0
OE
_
JS
J 1
DI
D S
JS
J 0
DI
D S
JS
J 1
CL
C R
L
JS
J 0
CL
C R
O
O
JS
J 1
M
E
D
O
JS
J 0
M
E
D
N
N
N
N
I T
N
U
A D
S
J 1
S
J 0
N
I
JS
N
I T
h
0
0
0
0
Note: all register bits are
read/write
except for AUDINT, JSINT, JS0 and JS1, which are
read only
.
JSINT
Indicates that a jack sense interrupt has been generated by JS0 or JS1. Remains set until all JS enabled interrupts
are cleared.
JS0
Indicates Pin JS0 state.
JS1
Indicates Pin JS1 state.
AUDINT
Indicates the Codec has generated audio interrupt. Remains set until software clears all pending interrupts.
JS0MODE
Sets JS0 pin input mode, 1 = Interrupt 0 = Jack Sense.
JS1MODE
Sets JS1 pin input mode, 1 = Interrupt 0 = Jack Sense.
JS0CLR
This bit is set by the Codec when there is a pending JS0 interrupt. Software must clear this bit to clear the JS0
interrupt status bit.
JS1CLR
This bit is set by the Codec when there is a pending JS1 interrupt. Software must clear this bit to clear the JS1
interrupt status bit.
JS0DIS
If the JS0DIS bit is set, the Codec ignores Jack Sense pin JS0.
JS1DIS
If the JS1DIS bit is set, the Codec ignores Jack Sense pin JS1.
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