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參數(shù)資料
| 型號： | AD1879 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | IR Emitting Diode; Power Dissipation, Pd:50mW; Viewing Angle:45 ; Package/Case:SIP; Operating Temperature Range:-25 C to +85 C; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| 中文描述： | 18-BIT CONVERTER SUBSYSTEM ADC, SERIAL ACCESS, PDIP28 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 628K |
| 代理商： | AD1879 |
AD1878/AD1879
REV. 0
–10–
In the “slave modes,” the bit clock (BCK ), the word clock
(WCK ), and the left/right clock (L
R
CK ) are user-supplied in-
puts. Note that, for performance reasons, the AD1878/AD1879
does not support asynchronous operation; these clocks must be
externally derived from the master clock (CLOCK ). T he func-
tional sequence of the signals in the slave modes is identical to
the master modes with word clock input, and they share the
same sequence timing diagrams.
In 64-Bit Master Mode with Word Clock Output, the 16-/18-bit
words are right-justified in 32-bit fields as shown in Figures 7
and 8. T he WCK output goes HI approximately with the falling
edge of the BCK output, indicating that the MSB on DAT A will
be externally valid at the next BCK rising edge. T he L
R
CK out-
put discriminates the left from the right output fields.
In 64-bit frame modes with word clock (WCK ) is an input, the
16-/18-bit words can be placed in user-defined locations within
32-bit fields. T his is true in both master and slave modes. T he
options are illustrated in Figures 9, 10, 11, and 12. For all op-
tions, the first occurrence in a 32-bit field when the word clock
(WCK ) is HI on a bit clock (BCK ) falling edge will cause the
beginning of data transmission. T he MSB on DAT A will be
valid at the next BCK rising edge. Again, the L
R
CK output dis-
criminates the left from the right output fields.
Figure 9 illustrates the general case for 64-bit frame modes with
word clock input where the MSB is valid on the rising edge of
the Nth bit clock (BCK ). Figures 10 and 11 illustrate the limits.
If WCK is still LO at the falling edge of the 14th bit clock (BCK )
for the AD1879 or 16th bit clock (BCK ) for the AD1878, then the
MSB of the current word will be output anyway, valid at the ris-
ing edge of the 15th bit clock (BCK ) in the field for the AD1879,
17th for the AD1878. T his limit insures that all 16/18 bits will
be output within the current field. T he effect is to right-justify
the data.
32
1
2
3
14
15
16
17
18
29
32
1
2
3
14
15
16
17
18
1
MSB MSB–1 MSB–2 MSB–3
LEFT DATA
ZEROS
LSB–3
LSB
LSB
MSB MSB–1 MSB–2MSB–3
RIGHT DATA
30
31
ZEROS
LSB–2 LSB–1
29
32
LSB–3
LSB
30
31
LSB–2 LSB–1
BCK
OUTPUT
WCK
OUTPUT
LRCK
OUTPUT
PREVIOUS DATA
DATA
OUTPUT
Figure 7. AD1879 64-Bit Output Timing with WCK as Output (Master Mode Only)
32
BCK
OUTPUT
1
2
3
14
15
16
17
18
29
32
1
2
3
14
15
16
17
18
1
WCK
OUTPUT
30
31
LRCK
OUTPUT
29
32
30
31
MSB MSB–1
LEFT DATA
ZEROS
LSB–3
LSB
PREVIOUS DATA
DATA
OUTPUT
RIGHT DATA
ZEROS
LSB
LSB–1
LSB–2
MSB MSB–1
LSB–3
LSB
LSB–1
LSB–2
Figure 8. AD1878 64-Bit Frame Output Timing with WCK as Output (Master Mode Only)
LSB2
LSB
32
BCK I/O
1
N–1
N
N+1
31
32
WCK INPUT
AD1879
DATA OUTPUT
MSB–1
ZEROS
LSB–3
LRCK I/O
N+14
N+17
N+15 N+16
LSB–1
1
N–1
N
N+1
31
32
1
MSB MSB–1
ZEROS
ZEROS
LSB
LSB–3 LSB2 LSB–1
AD1878
DATA OUTPUT
MSB MSB–1
ZEROS
LSB–1
LSB
MSB MSB–1
ZEROS
ZEROS
LSB–1
LSB
N+14
N+17
N+15 N+16
RIGHT DATA
RIGHT DATA
LEFT DATA
MSB
LEFT DATA
Figure 9. AD1878/AD1879 64-Bit Frame Output Timing with WCK as Input: WCK Transitions HI Before 16th BCK
(AD1878)/14th BCK (AD1879) (Master Mode or Slave Mode)
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD1881A | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC’97 SoundMAX Codec |
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