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參數(shù)資料
| 型號： | AD1878 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | High Performance 16-/18-Bit Stereo ADCs |
| 中文描述： | 16-BIT CONVERTER SUBSYSTEM ADC, SERIAL ACCESS, PDIP28 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 628K |
| 代理商： | AD1878 |
AD1878/AD1879
REV. 0
–8–
RIGHT INPUT
NE5532 OR OP-275
100pF
.1μF
5.76k
100pF
V
CC
V
SS
249k
100k
249k
V
SS
.1μF
.0047 μF
NPO
.01μF
NPO
.01μF
NPO
NE5532 OR
OP-275
VINR–
VINR+
VINL+
VINL–
12
13
16
17
REFR
REFL
10μF
14
.1μF
AD1878/79
LEFT
INPUT
100pF
100pF
V
CC
.1μF
.0047 μF
NPO
.01μF
NPO
NE5532 OR
OP-275
.1μF
V
CC
V
SS
.1μF
.01μF
NPO
10μF
15
5.62k
5.62k
5.62k
5.62k
5.49k
51
51
200
249k
5.62k
100k
5.36k
200
51
51
5.62k
5.62k
5.62k
249k
5.90k
Figure 2. AD1878/AD1879 Recommended Input Structure
V
CC
AGND
V
SS
V
DD
DGND
0.1μF
22μF
7805
IN
OUT
GND
+5V ANALOG
–5V
ANALOG
+5V DIGITAL
+12V < V
CC
< +18V
–12V > V
SS
> – 18V
0.1μF
22μF
0.1μF
22μF
7905
IN
OUT
GND
0.1μF
10μF
0.1μF
10μF
Figure 3. AD1878/AD1879 Recommended Power Condi-
tioning Circuit (If
±
5 V Supplies Are Not Already Available)
T he trim potentiometers shown in Figure 2 connecting the
minus (–) inputs of the driving op amps permit trimming out dc
offset, if desired.
Note that the driving op amp feedback resistors are all slightly
different values. T hese values produce a slight differential gain
imbalance and were derived empirically to minimize second
harmonic distortion on average and produce the best overall
T HD without part-by-part trimming. Replacing one of these
feedback resistors in each channel with a trim potentiometer
allows trimming the differential gain imbalance for part-by-part
optimal performance. We have done this in the lab by parallel-
ing 100 k
trim potentiometers around the 5.49 k
and
5.36 k
input feedback resistors for the V
IN
plus (+) signals
that can be found in Figure 2. By trimming gain imbalance, sec-
ond harmonic distortion can always be eliminated. In “Specifi-
cations,” a distinction is drawn between trimmed and untrimmed
signal-to (noise + distortion) and trimmed and untrimmed total
harmonic distortion. T he untrimmed specifications are tested to
the input structure shown in Figure 2. T he trimmed specifica-
tions are based on a part-by-part trim of this differential gain to
eliminate the second harmonic.
T he input circuit
of Figure 2 could be implemented with a
single pair of operational amplifiers per channel, one inverting
and one noninverting. T he recommended architecture shown in
Figure 2 using three inverting op amps per channel provides iso-
lation of the op amp inputs from charge dumped back from the
AD1878/AD1879’s input capacitors when these large capacitors
switch. T he performance from a two op amp per channel input
structure is not quite as good as the structure recommended,
but it is close and may be adequate in many applications.
Layout and Decoupling Considerations
Obtaining the best possible performance from a state-of-the-art
data converter like the AD1878/AD1879 requires close atten-
tion to board layout. From extensive experimentation, we have
discovered principles that produce typical values of 103 dB dy-
namic range and 98 dB S/(T HD+N) in your system. Schematics
of our AD1878/AD1879 Evaluation Board, which implements
these recommendations, are available from Analog Devices.
T he principles and their rationales are listed below in descend-
ing order of importance. T he first two pertain to bypassing and
are illustrated in Figure 4.
AD1878/ 79
AV
SS
1 AV
SS
1 AV
DD
1 AGND AGND
10μF
–5V
ANALOG
+5V
ANALOG
10μF
0.1μF
+5V
DIGITAL
10μF
0.1μF
+5V
DIGITAL
AV
SS
2 AV
DD
2 DV
DD
DGND DGND DV
DD
9
20
5
–5V
ANALOG
+5V
ANALOG
+5V DIGITAL
OSCILLATOR
0.1μF
26
CLKIN
10μF
10μF
8
21
19
10
18
6
23
22
Figure 4. AD1878/AD1879 Recommended Bypassing and
Oscillator Circuits
T he digital bypassing of the AD1878/AD1879 is the most
critical
item on the board layout. T here are two pairs of digi-
tal supply pins of the part, each pair on opposite sides (Pins 5
and 6 and Pins 22 and 23). T he user should tie a bypass ca-
pacitor set (0.1
μ
F ceramic and 10
μ
F tantalum) on EACH
pair of supply pins as close to the pins as possible. T he traces
between these package pins and the capacitors should be as
short and as wide as possible. T his will prevent digital supply
current transients from being inductively transmitted to the
inputs of the part.
T he analog input bypassing is the second most critical item.
Use 0.01
μ
F NPO ceramic
capacitors from each input pin to
the analog ground plane, with a clear ground path from the
bypass capacitor to the AGND pin on the same side of the
package (Pins 10 and 18). T he trace between this package
pin and the capacitor should be as short and as wide as pos-
sible. A 0.0047
μ
F NPO ceramic
capacitor should be placed
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1879 | IR Emitting Diode; Power Dissipation, Pd:50mW; Viewing Angle:45 ; Package/Case:SIP; Operating Temperature Range:-25 C to +85 C; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| AD1879* | High Performance 16-/18-Bit ## Stereo ADCs |
| AD1881 | SNAPAKMAGNETICCIRCUITBREAKER |
| AD1881A | AC’97 SoundMAX Codec |
| AD1881AJST | AC’97 SoundMAX Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1878JD | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 16-/18-Bit Stereo ADCs |
| AD1879 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 16-/18-Bit Stereo ADCs |
| AD1879JD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1881 | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC’97 SoundMAX Codec |
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