- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1978 > AD1871YRSZ-REEL (Analog Devices Inc)IC ADC STEREO 24BIT 96KHZ 28SSOP PDF資料下載
參數(shù)資料
| 型號： | AD1871YRSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC STEREO 24BIT 96KHZ 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 96k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
AD1871
–20–
REV. 0
The SPI compatible control port features four signals (CCLK,
CLATCH, CDATA, and COUT). The CLATCH signal is an
enable line that must be low to allow communication to or from
the control port. The CCLK is the serial clock that clocks in
serial data via the CDATA pin and clocks out serial data via the
COUT pin. Figures 20 and 21 show details of the control port
timing.
Table II. Register Address Map
Address
Control Register
0000
Control Register I
0001
Control Register II
0010
Control Register III
0011
Peak Reading Register I
0100
Peak Reading Register II
DOU T
LRCLK
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
BCLK
DOU T
LEFT CH AN N EL
BCLK
MSB
–1
MSB
–2
LSB
+1
LSB
123
2 3
24
RI GH T CH AN N EL
123
2 3
2 4
MSB
–1
MSB
–2
LSB
+1
LSB
Figure 18. Cascade Mode Data Interface Timing
CI N
CLAT CH
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
CCLK
CI N
CCLK
MSB
–1
LSB
+1
LSB
Figure 19. Cascade Mode Control Port Timing
CONTROL/STATUS REGISTERS
The AD1871’s Operating Mode is set by programming three,
10-bit Control Registers via an SPI compatible port. Table III
details the format of the AD1871 control words, which are 16
bits wide with a 4-bit address field in Positions 15 through 12,
a Read/
Write Bit in Position 11, a Reserved Bit in Position 10,
and 10 bits of register data (corresponding to the control regis-
ter width) in Positions 9 through 0. The three control words
occupy Addresses 0000b through 0010b in the register map (see
Table II).
The AD1871 also features two readback (status) registers that
can be enabled to track the peak reading on each of the chan-
nels (left and right). These 6-bit results are read back via the
SPI compatible port in a 16-bit frame similar to that of the
control words.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1877JRZ-RL | IC ADC STEREO 16BIT 28-SOIC |
| AD1974YSTZ-RL | IC CODEC 4CH ADC W/PLL 48-LQFP |
| AD2S99BP | IC OSC SINUSOIDAL 20KHZ 20-PLCC |
| AD5310BRM | IC DAC 10BIT R-R W/BUFF 8-MSOP |
| AD5341BRUZ | IC DAC 12BIT SNGL VOUT 20TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1876 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit 100 kSPS Sampling ADC |
| AD1876JN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1877 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single-Supply 16-Bit Stereo ADC |
| AD1877JR | 制造商:Rochester Electronics LLC 功能描述:IC, +5V 16-BIT STEREO ADC - Bulk 制造商:Analog Devices 功能描述:IC +5V 16-BIT STEREO ADC |
| AD1877JR-REEL | 制造商:Rochester Electronics LLC 功能描述:SINGLE SUPPLY 5V 16-BIT STERO ADC - Tape and Reel 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。