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參數(shù)資料
| 型號： | AD1859JRS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Stereo, Single-Supply 18-Bit Integrated DAC |
| 中文描述： | SERIAL INPUT LOADING, 18-BIT DAC, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 302K |
| 代理商： | AD1859JRS |
a
Stereo, Single-Supply
18-Bit Integrated
SD
DAC
AD1859
PRODUCT OVE RVIE W
T he AD1859 is a complete 16-/18-bit single-chip stereo digital
audio playback subsystem. It comprises a variable rate
digital
interpolation filter, a revolutionary multibit sigma-delta (
∑
)
modulator with dither, a jitter-tolerant DAC, switched capacitor
and continuous time analog filters, and analog output drive cir-
cuitry. Other features include an on-chip stereo attenuator and
mute, programmed through an SPI-compatible serial control
port.
T he key differentiating feature of the AD1859 is its asynchro-
nous master clock capability. Previous
∑
audio DACs re-
quired a high frequency master clock at 256 or 384 times the
intended audio sample rate. T he generation and management
of this high frequency synchronous clock is burdensome to the
board level designer. T he analog performance of conventional
single bit
∑
DACs is also dependent on the spectral purity of
the sample and master clocks. T he AD1859 has a digital Phase
Locked Loop (PLL) which allows the master clock to be asyn-
chronous, and which also strongly rejects jitter on the sample
clock (left/
right
clock). T he digital PLL allows the AD1859 to
be clocked with a single frequency (27 MHz for example) while
the sample frequency (as determined from the left/
right
clock)
can vary over a wide range. T he digital PLL will lock to the
new sample rate in approximately 100 ms. Jitter components
15 Hz above and below the sample frequency are rejected by
6 dB per octave. T his level of jitter rejection is unprecedented
in audio DACs.
T he AD1859 supports continuously variable sample rates with
essentially linear phase response, and with an option for external
analog de-emphasis processing. T he clock circuit includes an
on-chip oscillator, so that the user need only provide an external
crystal. T he oscillator may be overdriven, if desired, with an ex-
ternal clock source.
(
continued on page 7
)
*
SPI is a registered trademark of Motorola, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
Complete, Low Cost Stereo DAC System in a Single Die
Package
Variable Rate Oversampling Interpolation Filter
Multibit
SD
Modulator with Triangular PDF Dither
Discrete and Continuous Time Analog Reconstruction
Filters
Extremely Low Out-of-Band Energy
64 Step (1 dB/Step) Analog Attenuator with Mute
Buffered Outputs with 2 k
V
Output Load Drive
Rejects Sample Clock J itter
94 dB Dynamic Range, –88 dB THD+N Performance
Option for Analog De-emphasis Processing with
External Passive Components
6
0.1
8
Maximum Phase Linearity Deviation
Continuously Variable Sample Rate Support
Digital Phase Locked Loop Based Asynchronous Master
Clock
On-Chip Master Clock Oscillator, Only External Crystal
Is Required
Power-Down Mode
Flexible Serial Data Port (I
2
S-J ustified, Left-J ustified,
Right-J ustified and DSP Serial Port Modes)
SPI* Compatible Serial Control Port
Single +5 V Supply
28-Pin SOIC and SSOP Packages
APPLICATIONS
Digital Cable TV and Direct Broadcast Satellite Set-Top
Decoder Boxes
Digital Video Disc, Video CD and CD-I Players
High Definition Televisions, Digital Audio Broadcast
Receivers
CD, CD-R, DAT, DCC, ATAPI CD-ROM and MD Players
Digital Audio Workstations, Computer Multimedia
Products
FUNCT IONAL BLOCK DIAGRAM
INSERIAL
AD1859
16- OR INPUT
6
ASYNCHRONOUS
DE-EMPHASIS
COMMON MODE
ANALOG
DE-EMPHASIS
DE-EMPHASIS
MUTE
SUPPLY
2
FILTER AND
GROUND
CDATA
INPUT
2
3
2
DIGITAL
DOPOWER
MUTE
OUTPUT
DAC
RVOLTAGE
∑
MULTIBIT
VARIABLE RATE
DATA
INTERFACE
MUTE
OUTPUT
FILTER
DAC
∑
MULTIBIT
VARIABLE RATE
DMANAGER
FILTER
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1859JRS-REEL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 18-bit 28-Pin SSOP T/R |
| AD1859JRZ | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 18-bit 28-Pin SOIC W |
| AD1859JRZ-RL | 功能描述:IC DAC STEREO SGL SUPP 5V 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:2,400 系列:- 設(shè)置時間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| AD1860N | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1860N-J | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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