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參數(shù)資料
| 型號： | AD1837 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 2 ADC, 8 DAC, 96 kHz, 24-Bit Codec |
| 中文描述： | 2的ADC，8 DAC的，96千赫，24位編解碼器 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 523K |
| 代理商： | AD1837 |
REV. B
AD1837
–11–
FUNCTIONAL OVERVIEW
ADCs
There are two ADC channels in the AD1837, configured as a
stereo pair. Each ADC has fully differential inputs. The ADC
section can operate at a sample rate of up to 96 kHz. The ADCs
include on-board digital decimation filters with 120 dB stop-band
attenuation and linear phase response, operating at an over-
sampling ratio of 128 (for 48 kHz operation) or 64 (for 96 kHz
operation).
ADC peak level information for each ADC may be read from
the ADC Peak 0 and ADC Peak 1 registers. The data is supplied
as a 6-bit word with a maximum range of 0 dB to –63 dB and a
resolution of 1 dB. The registers will hold peak information until
read; after reading, the registers are reset so that new peak
information can be acquired. Refer to the register description
for details on the format. The two ADC channels have a common
serial bit clock and a left-right framing clock. The clock signals
are all synchronous with the sample rate.
The ADC digital pins, ABCLK and ALRCLK, can be set to
operate as inputs or outputs by connecting the
M
/S pin to
ODVDD or DGND, respectively. When the pins are set as
outputs, the AD1837 will generate the timing signals. When
the pins are set as inputs, the timing must be generated by the
external audio controller.
DACs
The AD1837 has eight DAC channels arranged as four inde-
pendent stereo pairs, with eight single-ended analog outputs for
improved noise and distortion performance. Each channel has
its own independently programmable attenuator, adjustable in
1024 linear steps. Digital inputs are supplied through four serial
data input pins (one for each stereo pair) and a common frame
(DLRCLK) and bit (DBLCK) clock. Alternatively, one of the
“packed data” modes may be used to access all eight channels
on a single TDM data pin. A stereo replicate feature is included
where the DAC data sent to the first DAC pair is also sent to the
other DACs in the part. The AD1837 can accept DAC data at a
sample rate of 192 kHz on DAC 1 only. The stereo replicate fea-
ture can then be used to copy the audio data to the other DACs.
Each of the output pins sits at a dc level of V
REF
and swings
±
1.4 V for a 0 dB digital input signal. A single op amp third
order external low-pass filter is recommended to remove high
frequency noise present on the output pins. Note that the use of
op amps with low slew rate or low bandwidth may cause high
frequency noise and tones to fold down into the audio band;
care should be exercised in selecting these components.
The FILTD pin should be connected to an external grounded
capacitor. This pin is used to reduce the noise of the internal
DAC bias circuitry, thereby reducing the DAC output noise. In
some cases, this capacitor may be eliminated with little effect
on performance.
DAC and ADC Coding
The DAC and ADC output data stream is in a twos complement
encoded format. The word width can be selected from 16-bit,
20-bit, or 24-bit. The coding scheme is detailed in Table I.
Table I. Coding Scheme
Code
Level
01111......1111
00000......0000
10000......0000
+FS
0 (Ref Level)
–FS
Clock Signals
The DAC and ADC engines in the AD1837 are designed to
operate from a 24.576 MHz internal master clock (IMCLK).
This clock is used to generate 48 kHz and 96 kHz sampling on
the ADC and 48 kHz, 96 kHz, and 192 kHz on the DAC,
although the 192 kHz option is available only on one DAC pair.
The stereo replicate feature can be used to copy this DAC data
to the other DACs if required.
To facilitate the use of different MCLK values, the AD1837
provides a clock scaling feature. The MCLK scaler can be
programmed via the SPI port to scale the MCLK by a factor of
1 (pass through), 2 (doubling), or 2/3. The default setting of
the MCLK scaler is 2, which will generate 48 kHz sampling
from a 12.288 MHz MCLK. Additional sample rates can be
achieved by changing the MCLK value. For example, the CD
standard sampling frequency of 44.1 kHz can be achieved using
an 11.2896 kHz MCLK. Figure 2 shows the internal configura-
tion of the clock scaler and converter engines.
DAC ENGINE
CLOCK SCALING
1
2/3
MCLK
12.288MHz
DAC INPUT
INTERPOLATION
FILTER
-
MODULATOR
DAC
48kHz/96kHz/192kHz
ADC OUTPUT
48kHz/96kHz
ANALOG
OUTPUT
ANALOG
INPUT
IMCLK = 24.576MHz
ADC ENGINE
OPTIONAL
HPF
DECIMATOR/
FILTER
-
MODULATOR
2
Figure 2. Modulator Clocking Scheme
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1837AS | 2 ADC, 8 DAC, 96 kHz, 24-Bit Codec |
| AD1837AS-REEL | 2 ADC, 8 DAC, 96 kHz, 24-Bit Codec |
| AD1838AASZ-REEL | 2 ADC, 6 DAC, 96KHZ 24 BIT CODEC |
| AD1838AASZ | CHOKE COIL 22UH 1300MA SMD |
| AD1838A | CHOKE COIL 15UH 1600MA SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1837A | 制造商:AD 制造商全稱:Analog Devices 功能描述:2 ADC, 8 DAC, 96 kHz, 24-Bit Codec |
| AD1837AAS | 制造商:Rochester Electronics LLC 功能描述: 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE CODEC I.C. - Bulk 制造商:Analog Devices 功能描述: |
| AD1837AAS-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:2 ADC, 8 DAC, 96 kHz, 24-Bit Codec |
| AD1837AASZ | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 8DAC 24-Bit 52-Pin MQFP 制造商:Analog Devices 功能描述:IC CODEC SMD 1837 MQFP52 |
| AD1837AASZ-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 8DAC 24-Bit 52-Pin MQFP T/R |
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