參數(shù)資料
型號： AD1836AS
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： COIL 33UH 700MA CHOKE SMD
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP52
封裝： PLASTIC, MQFP-52
文件頁數(shù)： 7/18頁
文件大?。?/td> 878K
代理商： AD1836AS
PRELIMINARY TECHNICAL DATA
REV. PrC
AD1836
–7–
PIN FUNCTION DESCRIPTIONS
PIN
No.
Mnemonic
In/Out
Description
1, 40
2
3
4
5
6
7
8
9
10, 15
11, 14, 28, 29
12
13
16
17
18
19
20
DVDD
CDATA
PD/RST
OUTLP3
OUTLN3
OUTLP2
OUTLN2
OUTLP1
OUTLN1
AVDD
AGND
FILTD
FILTR
ADC1INLP
ADC1INLN
ADC1INRP
ADC1INRN
ADC2INL+/CAPL2
I
I
I
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
Digital Power Supply. Connect to digital 5 V supply.
Serial Control Input
Power-Down Reset
DAC 3 (Left) Positive Output
DAC 3 (Left) Negative Output
DAC 2 (Left) Positive Output
DAC 2 (Left) Negative Output
DAC 1 (Left) Positive Output
DAC 1 (Left) Negative Output
Analog Power Supply. Connect to analog 5 V.
Analog Ground
Filter Capacitor Connection. Recommend 10
μ
F//100 nF.
Voltage Reference Filter Capacitor Connection. Recommend 10
μ
F//100 nF.
ADC1 Left Positive Input
ADC1 Left Negative Input
ADC1 Right Positive Input
ADC1 Right Negative Input
ADC2 Left Positive Input (Direct Mode)/ADC2 Left Decoupling Cap
(MUX/PGA and PGA Differential Mode)
ADC2 Left Negative Input (Direct Mode)/ADC2 Left Decoupling Cap
(MUX/PGA and PGA Differential Mode)
ADC2 Left Input 2 (MUX/PGA Mode)/Left Positive Input (PGA Differ-
ential Mode)
ADC2 Left Input 1 (MUX/PGA Mode)/Left Negative Input (PGA Differ-
ential Mode)
ADC2 Right Input 1 (MUX/PGA Mode)/Right Negative Input (PGA
Differential Mode)
ADC2 Right Input 2 (MUX/PGA Mode)/Right Positive Input (PGA
Differential Mode)
ADC2 Right Negative Input (Direct Mode)/ADC2 Right Decoupling Cap
(MUX/PGA and PGA Differential Mode)
ADC2 Right Positive Input (Direct Mode)/ADC2 Right Decoupling Cap
(MUX/PGA and PGA Differential Mode)
DAC 1 (Right) Negative Output
DAC 1 (Right) Positive Output
DAC 2 (Right) Negative Output
DAC 2 (Right) Positive Output
DAC 3 (Right) Negative Output
DAC 3 (Right) Positive Output
LR Clock for DACs
Bit Clock for DACs
DAC Input #1 (Input to DAC1 and DAC2)
Digital Ground
DAC Input #2 (Input to DAC3 and DAC4)
DAC Input #3 (Input to DAC5 and DAC6)
Bit Clock for ADCs
LR Clock for ADCs
Master Clock Input
Digital Output Driver Power Supply
ADC Serial Data Output #1
ADC Serial Data Output #2
Output for Control Data
Latch Input for Control Data
Control Clock Input for Control Data
Digital Ground
21
ADC2INL–/CAPL1
I
22
ADC2INL1
I
23
ADC2INL2
I
24
ADC2INR2
I
25
ADC2INR1
I
26
ADC2INR–/CAPR1
I
27
ADC2INR+/CAPR2
I
30
31
32
33
34
35
36
37
38
39, 52
41
42
43
44
45
46
47
48
49
50
51
52
OUTRN1
OUTRP1
OUTRN2
OUTRP2
OUTRN3
OUTRP3
DLRCLK
DBCLK
DSDATA1
DGND
DSDATA2
DSDATA3
ABCLK
ALRCLK
MCLK
ODVDD
ASDATA1
ASDATA2
COUT
CLATCH
CCLK
DGND
O
O
O
O
O
O
I/O
I/O
I
I
I
I
O
O
I
I
O
O
O
I
I
I
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