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參數(shù)資料
| 型號： | AD1835AS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 2 ADC, 8 DAC, 96 kHz, 24-Bit Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP52 |
| 封裝： | PLASTIC, MS-022AC, MQFP-52 |
| 文件頁數(shù)： | 12/23頁 |
| 文件大?。?/td> | 326K |
| 代理商： | AD1835AS |
REV. PrA
PRELIMINARY TECHNICAL DATA
AD1835
–12–
DAC ENGINE
CLOCK SCALING
1
2
2/3
MCLK
DAC I/P
INTERPOLATION
FILTER
Σ
-
MODULATOR
DAC
48kHz/96kHz/192kHz
ADC ENGINE
ADC O/P
OPTIONAL
HPF
DECIMATOR/
FILTER
48kHz/96kHz
ANALOG
OUTPUT
ANALOG
INPUT
12.288MHz
IMCLK = 24.576MHz
Σ
-
MODULATOR
Figure 2. Modulator Clocking Scheme
CLATCH
CCLK
CIN
COUT
D0
D8
D0
D15
D14
D9
D8
t
CCH
t
CCL
D9
t
CDS
t
CDH
t
CLS
t
CLH
t
COD
t
COTS
t
CCP
t
COE
Figure 3. Format of SPI Timing
RESET and Power-Down
PD/RST
will power down the chip and set the control regis-
ters to their default settings. After
PD/RST
is de-asserted, an
initialization routine will run inside the AD1835 to clear all
memories to zero. This initialization lasts for approximately
20 LRCLK intervals. During this time, it is recommended that
no SPI writes occur.
Power Supply and Voltage Reference
The AD1835 is designed for 5 V supplies. Separate power supply
pins are provided for the analog and digital sections. These pins
should be bypassed with 100 nF ceramic chip capacitors, as
close to the pins as possible, to minimize noise pickup. A bulk
aluminum electrolytic capacitor of at least 22
μ
F should also be
provided on the same PC board as the codec. For critical appli-
cations, improved performance will be obtained with separate
supplies for the analog and digital sections. If this is not
possible, it is recommended that the analog and digital supplies
be isolated by means of two ferrite beads in series with the by-
pass capacitor of each supply. It is important that the analog
supply be as clean as possible.
The internal voltage reference is brought out on the FILTR pin
and should be bypassed as close as possible to the chip, with a
parallel combination of 10
μ
F and 100 nF. The reference volt-
age may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the V
REF
pin should be limited to less than 50
μ
A.
Serial Control Port
The AD1835 has an SPI-compatible control port to permit
programming the internal control registers for the ADCs and
DACs and for reading the ADC signal levels from the internal
peak detectors. The SPI control port is a 4-wire serial control port.
The format is similar to the Motorola SPI format except the
input data-word is 16 bits wide. The maximum serial bit clock
frequency is 12.5 MHz and may be completely asynchronous to
the sample rate of the ADCs and DACs. Figure 3 shows the
format of the SPI signal.
Serial Data Ports—Data Format
The ADC serial data output mode defaults to the popular I
2
S
format, where the data is delayed by 1 BCLK interval from the
edge of the LRCLK. By changing Bits 6 to 8 in ADC Control
Register 2, the serial mode can be changed to Right-Justified
(RJ), Left-Justified DSP (DSP), or Left-Justified (LJ). In the RJ
mode, it is necessary to set Bits 4 and 5 to define the width of
the data-word.
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PDF描述 |
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| AD1836ACSRL | Multichannel 96 kHz Codec |
| AD1836AAS | Multichannel 96 kHz Codec |
| AD1836AASRL | Direct-Conversion TV Tuner |
| AD1836ACS | Direct-Conversion TV Tuner |
| AD1836A | Multichannel 96 kHz Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1835AS-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 8DAC 24-Bit 52-Pin MQFP T/R |
| AD1836 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multichannel 96 kHz Codec |
| AD1836A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multichannel 96 kHz Codec |
| AD1836AAS | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 3DAC 24-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI CHANNEL 96 KHZ CODEC - Bulk 制造商:Analog Devices 功能描述:IC CODEC 96KHZ SMD 1836 MQFP52 |
| AD1836AASRL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 3DAC 24-Bit 52-Pin MQFP T/R |
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