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參數(shù)資料
| 型號： | AD1833AAST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| 中文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PQFP48 |
| 封裝： | 1.40 MM HEIGHT, LOW PROFILE, PLASTIC, MS-026BBC, QFP-48 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 687K |
| 代理商： | AD1833AAST |
REV. 0
AD1833A
–11–
DAC Word Width
The AD1833A will accept input data in three separate word-
lengths—16 bits, 20 bits, and 24 bits. The word length may be
selected by writing to Control Bits 4 and 3 in DAC Control
Register 1 (see Table V).
Table V. Word Length Settings
Bit 4
Bit 3
Word Length
0
0
1
1
0
1
0
1
24 Bits
20 Bits
16 Bits
Reserved
Power-Down Control
The AD1833A can be powered down by writing to Control Bit 2
in DAC Control Register 1 (see Table VI).
Table VI. Power-Down Control
Bit 2
Power-Down Setting
0
1
Normal Operation
Power-Down Mode
Interpolator Mode
The AD1833A’s DAC interpolators can be operated in one of
three modes—8 , 4
,
or 2 — then correspond to 48 kHz, 96kHz,
and 192 kHz modes, respectively
(for IMCLK = 24.576 MHz). The
interpolator mode may be selected by writing to Control Bits 1
and 0 in DAC Control Register 1 (see Table VII).
Table VII. Interpolator Mode Settings
Bit 1
Bit 0
Interpolator Mode
0
0
1
1
0
1
0
1
8x (48 kHz)
*
2x (192 kHz)
*
4x (96 kHz)
*
Reserved
*
For IMCLK = 24.576 MHz.
DAC CONTROL REGISTER 1
De-emphasis
The AD1833A has a built-in de-emphasis filter that can be used
to decode CDs that have been encoded with the standard
Redbook 50
m
s/15
m
s emphasis response curve. Three curves are
available, one each for 32 kHz, 44.1 kHz, and 48 kHz sampling
rates. The filters may be selected by writing to Control Bits 9
and 8 in DAC Control Register 1 (see Table III).
Table III. De-emphasis Settings
Bit 9
Bit 8
De-emphasis
0
0
1
1
0
1
0
1
Disabled
44.1 kHz
32 kHz
48 kHz
Data Serial Interface Mode
The AD1833A’s serial data interface is designed to accept data
in a wide range of popular formats including I
2
S, right-justified
(RJ), left-justified (LJ), and flexible DSP modes. The L/RCLK
pin acts as the word clock (or frame sync) to indicate sample
interval boundaries. The BCLK defines the serial data rate
while the data is input on the SDIN1–SDIN3 pins. The serial
mode settings may be selected by writing to Control Bits 7
through 5 in the DAC Control Register 1 (see Table IV).
Table IV. Data Serial Interface Mode Settings
Bit 7
Bit 6
Bit 5
Serial Mode
I
2
S
Right Justify
DSP
Left Justify
Packed Mode 1 (256)
Packed Mode 2 (128)
TDM Mode
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table II. DAC Control Register 1
Function
Data-Word
Width
Power-Down
RESET
Interpolator
Mode
Address
Reserved
1
De-emphasis
Serial Mode
15–12
11
10
9–8
7–5
000 = I
2
S
001 = RJ
010 = DSP
011 = LJ
100 = Pack Mode 1 (256)
101 = Pack Mode 2 (128)
110 = TDM Mode
111 = Reserved
4–3
2
1–0
0000
0
0
00 = None
01 = 44.1 kHz
10 = 32.0 kHz
11 = 48.0 kHz
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
0 = Normal
1 = PWRDWN
00 = 8
01 = 2
10 = 4
11 = Reserved
(48 kHz)
2
(192 kHz)
2
(96 kHz)
2
NOTES
1
Must be programmed to zero.
2
For IMCLK = 24.576 MHz.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1833ACST | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD1833ACST-REEL | 24-Bit, 192 kHz, DAC |
| AD1833AAST-REEL | 24-Bit, 192 kHz, DAC |
| AD1833 | Multichannel 24-Bit, 192 kHz, DAC |
| AD1833AST | Multichannel 24-Bit, 192 kHz, DAC |
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