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參數(shù)資料
| 型號(hào)： | AD1833 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Multichannel 24-Bit, 192 kHz, DAC |
| 中文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 419K |
| 代理商： | AD1833 |
REV. 0
AD1833
–12–
I
2
S Timing
I
2
S timing uses an L/
R
CLK to define when the data being trans-
mitted is for the left channel and when it is for the right channel.
The L/
R
CLK is low for the left channel and high for the right
channel. A bit clock running at 64
×
f
S
is used to clock in the
data. There is a delay of one bit clock from the time the L/
R
CLK
signal changes state to the first bit of data on the SDINx lines.
The data is written MSB first and is valid on the rising edge of
bit clock.
Left Justified Timing
Left Justified (LJ) timing uses an L/
R
CLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/
R
CLK is high for the left channel and
low for the right channel. A bit clock running at 64
×
f
S
is used
to clock in the data. The first bit of data appears on the SDINx
lines at the same time the L/
R
CLK toggles. The data is written
MSB first and is valid on the rising edge of bit clock.
Right Justified Timing
Right Justified (RJ) timing uses an L/
R
CLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/
R
CLK is high for the left channel and
low for the right channel. A bit clock running at 64
×
f
S
is used
to clock in the data. The first bit of data appears on the SDINx
8-bit clock periods (for 24-bit data) after L/
R
CLK toggles. In RJ
mode the LSB of data is always clocked by the last bit clock
before L/
R
CLK transitions. The data is written MSB first and
is valid on the rising edge of bit clock.
LEFT CHANNEL
RIGHT CHANNEL
+1
LSB
MSB
L/
R
CLK
INPUT
BCLK
INPUT
SDATA
INPUT
+2
–
2
–
1
MSB
+1
LSB
+2
–
2
–
1
MSB
Figure 4. I
2
S Timing Diagram
LEFT CHANNEL
RIGHT CHANNEL
+1
LSB
L/
R
CLK
INPUT
BCLK
INPUT
SDATA
INPUT
+2
–
2
–
1
MSB
+1
LSB
+2
–
2
–
1
MSB
–
1
MSB
Figure 5. Left-Justified Timing Diagram
LEFT CHANNEL
RIGHT CHANNEL
+1
LSB
L/
R
CLK
INPUT
BCLK
INPUT
SDATA
INPUT
+2
–
2
–
1
LSB
MSB
+1
LSB
+2
–
2
–
1
MSB
Figure 6. Right-Justified Timing Diagram
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PDF描述 |
|---|---|
| AD1833AST | Multichannel 24-Bit, 192 kHz, DAC |
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| AD1835AS | 2 ADC, 8 DAC, 96 kHz, 24-Bit Codec |
| AD1836ACSRL | Multichannel 96 kHz Codec |
| AD1836AAS | Multichannel 96 kHz Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1833A | 制造商:AD 制造商全稱:Analog Devices 功能描述:24-Bit, 192 kHz, DAC |
| AD1833AAST | 制造商:Rochester Electronics LLC 功能描述:6 CHANNEL 24 BIT 192 KHZ DAC I.C. - Bulk 制造商:Analog Devices 功能描述:IC 24BIT DAC SMD 1833 LQFP48 |
| AD1833AAST-REEL | 制造商:Analog Devices 功能描述:DAC 6-CH Delta-Sigma 24-bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:6 CHANNEL 24 BIT 192 KHZ DAC I.C. - Tape and Reel |
| AD1833AASTZ | 功能描述:IC DAC AUDIO 24BIT 6CH 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD1833AASTZKL1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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