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參數(shù)資料
| 型號： | AD1819BJST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | AC’97 SoundPort Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 245K |
| 代理商： | AD1819BJST |
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AD1819B
–19–
REV. 0
The AC-Link protocol provides for a special 16-bit time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time
slot within the current audio frame. A “1” in a given bit position of Slot 0 indicates that the corresponding time slot within the cur-
rent audio frame has been assigned to a data stream, and contains valid data. If a slot is “tagged” invalid, it is the responsibility of the
source of the data, (AD1819B for the input stream, AC’97 controller for the output stream), to stuff all bit positions with 0s during
that slot’s active time. The AD1819B stuffs all invalid slots with zeros and ignores invalid input slots.
Additionally, for power savings, all clock, sync, and data signals can be halted.
For multiple codec operations, the AD1819B supports an enhanced mode for communicating with up to two additional codecs. The
Slave 1 AD1819B codec uses Slots 5 and 6, while Slave 2 uses Slots 7 and 8 as shown in the following diagram.
SLAVE 1
1
2
3
4
5
6
7
8
9
10
11
12
SLOT # ....
SYNC
OUTGOING STREAMS
INCOMING STREAMS
TAG
RSRVD
RSRVD
RSRVD
CMD
CMD
PCM
PCM
PCM
LEFT
PCM
PCM
LEFT
PCM
TAG
RSRVD
RSRVD
RSRVD
PCM
PCM
PCM
PCM
PCM
LEFT
PCM
RIGHT
STATUS
DATA
STATUS
ADR
RSRVD
RSRVD
ENHANCED MODE
SLAVE 2
DATA PHASE
TAG
PHASE
Figure 9. Standard Bidirectional Audio Frame
AC-Link Audio Output Frame (SDATA_OUT)
The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting AD1819B’s DAC
inputs and control registers. As briefly mentioned earlier, each audio output frame supports up to twelve 20-bit outgoing data time
slots. Slot 0 is a special reserved time slot containing 16 bits that are used for AC-Link protocol infrastructure.
Within Slot 0 the first bit is a global bit (SDATA_OUT Slot 0, Bit 15), which flags the validity for the entire audio frame. If the
“Valid Frame” bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. The next 12-bit
positions sampled by AC’97 indicate which of the corresponding 12 time slots contain valid data. In this way input DAC data
streams of differing sample rates can be transmitted across the AC-Link at its fixed 48 kHz audio frame rate. The following diagram
illustrates the time-slot-based AC-Link protocol.
END OF PREVIOUS
AUDIO FRAME
TIME SLOT “VALID”
BITS
(1) = TIME SLOT CONTAINS VALID PCM DATA
TAG PHASE
20.8
m
s (48kHz)
DATA PHASE
SLOT 1
SLOT 2
SLOT 3
SLOT 12
SYNC
BIT_CLK
CODEC
READY
SLOT(1) SLOT(2)
SLOT(12)
“0”
“0”
“0”
19
0
19
0
0
0
19
19
12.2888MHz
81.4ns
SDATA_IN
Figure 10. AC-Link Audio Output Frame
A new audio output frame begins with a low-to-high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On
the immediately following falling edge of BIT_CLK, the AD1819B samples the assertion of SYNC. This falling edge marks the time
when both sides of AC-Link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC’97 controller
transitions SDATA_OUT into the first bit position of Slot 0 (Valid Frame Bit). Each new bit position is presented to AC-Link on a
rising edge of BIT_CLK, and subsequently sampled by AD1819B on the following falling edge of BIT_CLK. This sequence ensures
that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
相關(guān)PDF資料 |
PDF描述 |
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| AD1819 | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD1819B | AC’97 SoundPort Codec |
| AD1833A | 24-Bit, 192 kHz, DAC |
| AD1833AAST | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD1833ACST | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1819BJST-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 48-Pin LQFP T/R |
| AD1819BJSTZ | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 48-Pin LQFP 制造商:Analog Devices 功能描述:Audio CODEC IC |
| AD1819BJSTZ-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 48-Pin LQFP T/R |
| AD1819JST | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Soundcard Circuits |
| AD182 | 制造商:Thomas & Betts 功能描述:NON-INS FEM-187 DISC 22-18 LEN .64 制造商:Thomas & Betts 功能描述:Quick Disconnect Terminal 18-22AWG F 21.08mm 5.84mm Tin |
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