參數(shù)資料
型號： AD1816AJST
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： SoundPort Controller
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： TQFP-100
文件頁數(shù)： 18/52頁
文件大?。?/td> 477K
代理商： AD1816AJST
AD1816A
–18–
REV. A
T able I. DSP Port T ime Slot Map
T ime Slot
SDI Pin
SDO Pin
0
1
2
3
4
5
6
7
8
9
10
11
Control Word Input
Control Register Data Input
* SS/SB ADC Right Input (to ISA)
* SS/SB ADC Left Input (to ISA)
* SS/SB DAC Right Input (to Codec)
* SS/SB DAC Left Input (to Codec)
* FM DAC Right Input (to Codec)
* FM DAC Left Input (to Codec)
* I
2
S (1) DAC Right Input (to Codec)
* I
2
S (1) DAC Left Input (to Codec)
* I
2
S (0) DAC Right Input (to Codec)
* I
2
S (0) DAC Left Input (to Codec)
Status Word Output
Control Register Data Output
SS/SB ADC Right Output (from Codec)
SS/SB ADC Left Output (from Codec)
SS/SB DAC Right Output (from ISA)
SS/SB DAC Left Output (from ISA)
FM DAC Right Output (from FM Synth Block)
FM DAC Left Output (from FM Synth Block)
I
2
S (1) DAC Right Output (from I
2
S Port (1))
I
2
S (1) DAC Left Output (from I
2
S Port (1))
I
2
S (0) DAC Right Output (from I
2
S Port (0))
I
2
S (0) DAC Left Output (from I
2
S Port (0))
*T his data is ignored by the AD1816A unless the channel pair is in intercept mode (see below).
SS = Sound System Mode
SB = SoundBlaster Mode
At start-up (after pin reset), there are exactly 12 time slots per frame. T he frame rate will be 57,291 and 2/3 Hz (11MHz sclk/
[16 bits
×
12 slots]). Interfacing with an Analog Devices 21xx family DSP can be achieved by putting the ADSP-21xx in 24 slot per
frame mode, where the first 12 and second 12 slots in the ADSP-21xx frame are identical.
T he frame rate can be changed from its default by a write to the DFS(2:0) bits in register 33. Rate choices are: Maximum (57,291
and 2/3 Hz default), SS capture rate, SS playback rate, FM rate, I
2
S Port (1) rate, or I
2
S Port (0) rate. When the frame rate is less
than 57,261 and 2/3 Hz, extra SCLK periods are added to fill up the time. T he number of SCLK periods added will vary somewhat
from frame to frame.
T o control the sample data flow of each channel through the DSP Port, valid input, valid output and request bits are located in the
control and status words. If the specified channel sample rate is equal to the frame rate, these bits may be ignored since they will
always be set to “1.”
By default, the DSP serial port allows only codec sample data I/O to be monitored. Intercept modes must be enabled to make substi-
tutions in sample data flow to and from the codec. T here are five bits in SS register 33, which enable intercept mode for SS capture,
SS playback, FM playback, I
2
S Port (1) playback and I
2
S Port (0) playback.
Control Word Input (Slot 0 SDI)
15
14
RES
6
R/W
13
RES
5
12
11
10
9
8
FCL R
7
ALIVE
SSCVI
4
SSPVI
3
IA[5:0]
FMVI
2
IS1VI
1
IS0VI
0
IA [5:0]
Indirect Register Address. Sound System Indirect Register Address defines the address of indirect registers shown
in T able VI.
Read/Write request. Either a read from or a write to an SS indirect register occurs every frame. Setting this bit ini-
tiates an SS indirect register read while clearing this bit initiates an SS indirect register write.
DSP port alive bit. When set, this bit indicates to the power-down timer that the DSP port is active. When cleared,
this bit indicates that the DSP port is inactive.
I
2
S Port 0 Substitution Data Input Valid Flag. T his bit is ignored if: (1) Intercept mode is not enabled for the I
2
S
port 0 channel pair, or (2) T he AD1816A did not request data from the I
2
S port 0 channel pair in the previous
frame. Otherwise, setting this bit indicates that slots 10 and 11 contain valid right and left I
2
S Port 0 substitution
data. When this bit is cleared, data in slots 10 and 11 is ignored.
I
2
S Port 1 Substitution Data Input Valid Flag. T his bit is ignored if: (1) Intercept mode is not enabled for I
2
S port
1 channel pair or (2) T he AD1816A did not request data from the I
2
S port channel pair in the previous frame.
Otherwise, setting this bit indicates that Slots 8 and 9 contain valid right and left I
2
S Port 1 substitution data.
When this bit is cleared, data in slots 8 and 9 is ignored.
FM Synthesis Substitution Data Input Valid Flag. T his bit is ignored if: (1) Intercept mode is not enabled for the
FM synthesis channel pair or (2) T he AD1816A did not request data from the FM synthesis channel pair in the
previous frame (see the FMRQ Bit 9 in the status word output). Otherwise, setting this bit to 1 indicates that slots
6 and 7 contain valid right and left FM synthesis channel substitution data. When this bit is reset to 0, data in slots
6 and 7 is ignored.
R/W
ALIVE
IS0VI
IS1VI
FMVI
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