參數(shù)資料
型號(hào)： AD1812JST
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： Silver Mica Capacitor; Capacitance:12pF; Capacitance Tolerance: 5%; Series:CD17; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.9mm; Leaded Process Compatible:No RoHS Compliant: No
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝： TQFP-160
文件頁(yè)數(shù)： 11/20頁(yè)
文件大?。?/td> 339K
代理商： AD1812JST
AD1812
REV. 0
–11–
Modem Interface Signals
Pin Name
P/TQFP
I/O
Description
MODEM_IRQ
38
I
Modem IRQ. The external modem asserts this pin HI to indicate a pending inter-
rupt. The AD1812 converts this signal to the appropriate interrupt in either Plug
and Play (LDN = 5) or Non-Plug and Play mode.
Modem Enable. When this pin is asserted (HI), the AD1812 enables the logical
device (LDN = 5) for an external modem chipset. Otherwise, LDN = 5 does not
exist. The state of this pin should not be altered after reset.
Modem Select. This active LO pin is a chip select for an external modem chipset.
The AD1812 decodes the (Plug & Play or Non-Plug and Play) configured ISA
bus address. AEN must be LO before asserting the MODEM_SEL pin.
MODEM_EN
39
I
MODEM_SEL
118
O
Game Port
Pin Name
P/TQFP
I/O
Description
A_1
A_2
A_X
A_Y
B_1
B_2
B_X
B_Y
41
42
46
47
43
44
48
49
I
I
I
I
I
I
I
I
Game Port A, Button #1.
Game Port A, Button #2.
Game Port A X-Axis.
Game Port A Y-Axis.
Game Port B, Button #1.
Game Port B, Button #2.
Game Port B X-Axis.
Game Port B Y-Axis.
MIDI Interface Signals
Pin Name
P/TQFP
I/O
Description
MIDI_IN
MIDI_OUT
31
96
I
O
RXD MIDI Input.
TXD MIDI Output.
Miscellaneous
Pin Name
P/TQFP
I/O
Description
PNP
37
I
Plug and Play Select. When this pin is asserted (HI), the Plug and Play
mode is enabled. If PnP is LO, the AD1812 operates in legacy mode, and
the Plug and Play configuration is disabled.
14.31818 MHz Crystal Output.
14.31818 MHz Clock Input, can be OSC from the ISA bus.
Power Down Signal. Active LO.
Voltage Reference.
Voltage Reference Filter.
Left Channel Filter Input.
Right Channel Filter Input.
External Control 0. The state of this pin (TTL HI or LO) is reflected in
codec indexed register 0x0A, Bit 6.
External Control 1. The state of this pin (TTL HI or LO) is reflected in
codec indexed register 0x0A, Bit 7.
Game Port Voltage Capacitor.
No Connect.
XTALO
XTALI
PWRDWN
VREF_X
VREF
L_FILT
R_FILT
XCTL0
30
29
36
60
59
54
53
95
O
I
I
O
I
I
I
O
XCTL1
159
O
GVC
NC
40
1–4, 81, 120–125,
156–158, 160
I
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