參數(shù)資料
型號(hào): AD1812JS
廠商: ANALOG DEVICES INC
元件分類: 消費(fèi)家電
英文描述: ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁(yè)數(shù): 16/20頁(yè)
文件大?。?/td> 339K
代理商: AD1812JS
AD1812
REV. 0
–16–
A detailed map of all direct and indirect register contents is summarized for reference as follows:
Table XVIII. Codec Direct Registers (16-Bit Interface)
Direct Address
WSS Base
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
res
res
res
res
Bit 8
res
Bit 7
INIT
Bit 6
MCE
Bit 5
TRD
Bit 4
IXA4
Bit 3
IXA3
Bit 2
IXA2
Bit 1
IXA1
Bit 0
IXA0
res
res
res
WSS Base+2
res
res
res
res
res
res
res
res
IXD7 IXD6 IXD5 IXD4 IXD3 IXD2 IXD1 IXD0
WSS Base+4
res
res
res
res
res
res
res
res
CU/L
CL/R CRDY SOUR PU/L
PL/R PRDY
INT
WSS Base+6 (read) CD15 CD14 CD13 CD12 CD11 CD10
CD9
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
WSS Base+6 (write) PD15 PD14 PD13 PD12 PD11 PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Table XIX. Codec Indirect Registers
Indirect Address
0x00
0x01
0x02
0x03
0x04
0x05
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
Bit 7
LSS1
RSS1
LMX1
RMX1
LMX2
RMX2
LDM
RDM
PFMT1
CPIO
XCTL1
COR
MID
DMA5
UB7
LB7
OL
LMME
LLM
RLM
TL7
TU7
FU7
FL7
res
V2
MIM
ADCPWD DACPWD MIXPWD
CFMT1
CFMT0
res
res
CUB7
CUB6
CLB7
CLB6
Bit 6
LSS0
RSS0
res
res
res
res
res
res
PFMT0
PPIO
XCTL0
PUR
res
DMA4
UB6
LB6
TE
RMME
res
res
TL6
TU6
FU6
FL6
TI
V1
MOM
Bit 5
LMGE
RMGE
res
res
res
res
LDA5
RDA5
PC/L
res
res
ACI
res
DMA3
UB5
LB5
LMG4
RMG4
res
res
TL5
TU5
FU5
FL5
CI
V0
res
Bit 4
res
res
LX1A4
RX1A4
LX2A4
RX2A4
LDA4
RDA4
PS/M
res
res
DRS
res
DMA2
UB4
LB4
LMG3
RMG3
LLG4
RLG4
TL4
TU4
FU4
FL4
PI
res
res
res
CS/M
res
CUB4
CLB4
Bit 3
LIG3
RIG3
LX1A3
RX1A3
LX2A3
RX2A3
LDA3
RDA3
PBSW
ACAL
res
ORR1
ID3
DMA1
UB3
LB3
LMG2
RMG2
LLG3
RLG3
TL3
TU3
FU3
FL3
CU
res
MIA3
res
CBSW
res
CUB3
CLB3
Bit 2
LIG2
RIG2
LX1A2
RX1A2
LX2A2
RX2A2
LDA2
RDA2
PINF8
SDC
res
ORR0
ID2
DMA0
UB2
LB2
LMG1
RMG1
LLG2
RLG2
TL2
TU2
FU2
FL2
CO
CID2
MIA2
res
CINF8
res
CUB2
CLB2
Bit 1
LIG1
RIG1
LX1A1
RX1A1
LX2A1
RX2A1
LDA1
RDA1
res
CEN
IEN
ORL1
ID1
res
UB1
LB1
LMG0
RMG0
LLG1
RLLG1
TL1
TU1
FU1
FL1
PO
CID1
MIA1
res
res
res
CUB1
CLB1
Bit 0
LIG0
RIG0
LX1A0
RX1A0
LX2A0
RX2A0
LDA0
RDA0
res
PEN
res
ORL0
ID0
DME
UB0
LB0
DACZ
res
LLG0
RLG0
TL0
TU0
FU0
FL0
PU
CID0
MIA0
res
res
TOTPWD
CUB0
CLB0
CC/L
res
CUB5
CLB5
Note that the only sticky bit in any of the Codec control registers is the interrupt (INT) bit. All other bits change with every sample
period.
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