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參數(shù)資料
| 型號： | AD1674J |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| 中文描述： | 12位100 kSPS的A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 255K |
| 代理商： | AD1674J |
AD1674
REV. C
–7–
PIN DE SCRIPT ION
Symbol
Pin No.
T ype
Name and Function
AGND
A
0
9
4
P
DI
Analog Ground (Common).
Byte Address/Short Cycle. If a conversion is started with A
0
Active LOW, a full 12-bit conversion
cycle is initiated. If A
0
is Active HIGH during a convert start, a shorter 8-bit conversion cycle
results. During Read (R/
C
= 1) with 12/
8
LOW, A
0
= LOW enables the 8 most significant bits
(DB4–DB11), and A
0
= HIGH enables DB3–DB0 and sets DB7–DB4 = 0.
Bipolar Offset. Connect through a 50
resistor to REF OUT for bipolar operation or to Analog
Common for unipolar operation.
Chip Enable. Chip Enable is Active HIGH and is used to initiate a convert or read operation.
Chip Select. Chip Select is Active LOW.
Data Bits 11 through 8. In the 12-bit format (see 12/
8
and A
0
pins), these pins provide the up-
per 4 bits of data. In the 8-bit format, they provide the upper 4 bits when A
0
is LOW and are
disabled when A
0
is HIGH.
Data Bits 7 through 4. In the 12-bit format these pins provide the middle 4 bits of data. In the
8-bit format they provide the middle 4 bits when Ao is LOW and all zeroes when A
0
is HIGH.
Data Bits 3 through 0. In the 12-bit format these pins provide the lower 4 bits of data. In the
8-bit format these pins provide the lower 4 bits of data when A
0
is HIGH, they are disabled
when A
0
is LOW.
Digital Ground (Common).
+10 V Reference Output.
Read/Convert. In the full control mode R/
C
is Active HIGH for a read operation and Active LOW
for a convert operation. In the stand-alone mode, the falling edge of R/
C
initiates a conversion.
Reference Input is connected through a 50
resistor to +10 V Reference for normal operation.
Status is Active HIGH when a conversion is in progress and goes LOW when the conversion is
completed.
+12 V/+15 V Analog Supply.
–12 V/–15 V Analog Supply.
+5 V Logic Supply.
10 V Span Input, 0 V to +10 V unipolar mode or –5 V to +5 V bipolar mode. When using the
AD1674 in the 20 V Span 10 V
IN
should not be connected.
20 V Span Input, 0 V to +20 V unipolar mode or –10 V to +10 V bipolar mode. When using
the AD1674 in the 10 V Span 20 V
IN
should not be connected.
T he 12/
8
pin determines whether the digital output data is to be organized as two 8-bit words
(12/
8
LOW) or a single 12-bit word (12/
8
HIGH).
BIP OFF
12
AI
CE
CS
DB11–DB8
6
3
27–24
DI
DI
DO
DB7–DB4
23–20
DO
DB3–DB0
19–16
DO
DGND
REF OUT
R/
C
15
8
5
P
AO
DI
REF IN
ST S
10
28
AI
DO
V
CC
V
EE
V
LOGIC
10 V
IN
7
11
1
13
P
P
P
AI
20 V
IN
14
AI
12/
8
2
DI
T YPE:
AI
AO =
DI
DO =
P
=
Analog Input
Analog Output
Digital Input
Digital Output
Power
=
=
FUNCT IONAL BLOCK DIAGRAM
REF OUT
SHA
COMP
AA
20k
AAA
10k
5k
2.5k
2.5k
5k
12
AD1674
AGND
BIP OFF
20V
IN
REF IN
10V
IN
IDAC
12
CONTROL
CE
R/C
12/8
CS
A
0
5k
10k
AA
SAR
CLOCK
AAA
10V
A
A
A
A
A
A
R
DAC
STS
DB11 (MSB)
DB0 (LSB)
PIN CONFIGURAT ION
TOP VIEW
(Not to Scale)
AD1674
18
28
27
24
23
22
26
25
21
20
19
17
16
15
13
1
2
5
6
7
3
4
8
9
10
12
14
V
LOGIC
12/8
CE
V
CC
A
0
REF OUT
AGND
REF IN
V
EE
BIP OFF
10V
IN
20V
IN
CS
R/C
STS
DB11(MSB)
DB10
DB8
DB7
DB6
DB9
DB5
DB4
DB3
DB2
DB1
DB0(LSB)
DGND
11
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PDF描述 |
|---|---|
| AD1674JN | 12-Bit 100 kSPS A/D Converter |
| AD1674JR | 12-Bit 100 kSPS A/D Converter |
| AD1674K | 12-Bit 100 kSPS A/D Converter |
| AD1674A | 12-Bit 100 kSPS A/D Converter |
| AD1674KN | 12-Bit 100 kSPS A/D Converter |
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