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參數(shù)資料
| 型號(hào)： | AD1674* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit 100 kSPS A/D Converter |
| 中文描述： | 12位100 kSPS的A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 255K |
AD1674
REV. C
–10–
Q
R
S
READ
S
R
Q
QB
VALUE OF A0 AT LAST
EOC 12
EOC 8
SAR RESET
1μs DELAY-HOLD SETTLING
1
μ
s DELAY-ACQUISITION
NYBBLE A
NYBBLE B
NYBBLE C
NYBBLE B = 0
TO OUTPUT
BUFFERS
CE
A0
12/8
R/C
CS
D
Q
QB
EN
D
Q
EN
CLK ENABLE
STATUS
HOLD/SAMPLE
Figure 10. Equivalent Internal Logic Circuitry
FULL-CONT ROL MODE
Chip Enable (CE), Chip Select (
CS
) and Read/ Convert (R/
C
)
are used to control Convert or Read modes of operation. Either
CE or
CS
may be used to initiate a conversion. T he state of R/
C
when CE and
CS
are both asserted determines whether a data
Read (R/
C
= 1) or a Convert (R/
C
= 0) is in progress. R/
C
should be LOW before both CE and
CS
are asserted; if R/
C
is
HIGH, a Read operation will momentarily occur, possibly
resulting in system bus contention.
ST AND-ALONE MODE
T he AD1674 can be used in a “stand-alone” mode, which is
useful in systems with dedicated input ports available and thus
not requiring full bus interface capability. Stand-alone mode
applications are generally able to issue conversion start com-
mands more precisely than full-control mode. T his improves ac
performance by reducing the amount of control-induced aper-
ture jitter.
In stand-alone mode, the control interface for the AD1674 and
AD674A are identical. CE and 12/
8
are wired HIGH,
CS
and
A
0
are wired LOW, and conversion is controlled by R/
C
. T he
three-state buffers are enabled when R/
C
is HIGH and a con-
version starts when R/
C
goes LOW. T his gives rise to two pos-
sible control signals—a high pulse or a low pulse. Operation
with a low pulse is shown in Figure 4a. In this case, the outputs
are forced into the high impedance state in response to the fall-
ing edge of R/
C
and return to valid logic levels after the conver-
sion cycle is completed. T he ST S line goes HIGH 200 ns after
R/
C
goes LOW and returns low 1
μ
s after data is valid.
If conversion is initiated by a high pulse as shown in Figure 4b,
the data lines are enabled during the time when R/
C
is HIGH.
T he falling edge of R/
C
starts the next conversion and the data
lines return to three-state (and remain three-state) until the next
high pulse of R/
C
.
CONVE RSION T IMING
Once a conversion is started, the ST S line goes HIGH. Convert
start commands will be ignored until the conversion cycle is
complete. T he output data buffers will be enabled a minimum
of 0.6
μ
s prior to ST S going LOW. T he ST S line will return
LOW at the end of the conversion cycle.
T he register control inputs, A
0
and 12/
8
, control conversion
length and data format. If a conversion is started with A
0
LOW,
a full 12-bit conversion cycle is initiated. If A
0
is HIGH during a
convert start, a shorter 8-bit conversion cycle results.
During data read operations, A
0
determines whether the three-
state buffers containing the 8 MSBs of the conversion result (A
0
= 0) or the 4 LSBs (A
0
= 1) are enabled. T he 12/
8
pin deter-
mines whether the output data is to be organized as two 8-bit
words (12/
8
tied LOW) or a single 12-bit word (12/
8
tied
HIGH). In the 8-bit mode, the byte addressed when A
0
is high
contains the 4 LSBs from the conversion followed by four trail-
ing zeroes. T his organization allows the data lines to be over-
lapped for direct interface to 8-bit buses without the need for
external three-state buffers.
INPUT CONNE CT IONS AND CALIBRAT ION
T he 10 V p-p and 20 V p-p full-scale input ranges of the
AD1674 accept the majority of signal voltages without the need
for external voltage divider networks which could deteriorate the
accuracy of the ADC.
T he AD1674 is factory trimmed to minimize offset, linearity,
and full-scale errors. In many applications, no calibration trim-
ming will be required and the AD1674 will exhibit the accuracy
limits listed in the specification tables.
In some applications, offset and full-scale errors need to be
trimmed out completely. T he following sections describe the
correct procedure for these various situations.
UNIPOLAR RANGE INPUT S
Figure 11 illustrates the external connections for the AD1674 in
unipolar-input mode. T he first output-code transition (from
0000 0000 0000 to 0000 0000 0001) should nominally occur
for an input level of +1/2 LSB (1.22 mV above ground for a 10 V
range; 2.44 mV for a 20 V range). T o trim unipolar offset to this
nominal value, apply a +1/2 LSB signal between Pin 13 and
ground (10 V range) or Pin 14 and ground (20 V range) and ad-
just R1 until the first transition is located. If the offset trim is
not required, Pin 12 can be connected directly to Pin 9; the two
resistors and trimmer for Pin 12 are then not needed.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1674A | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit 100 kSPS A/D Converter |
| AD1674AD | 功能描述:IC ADC SNGL 12BIT 28-CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD1674AR | 功能描述:IC ADC SNGL 12BIT 28SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD1674AR-REEL | 功能描述:IC ADC SNGL 12BIT 28SOIC T/R RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
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