- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373857 > AD1556 (Analog Devices, Inc.) 24-Bit ADC WITH LOW NOISE PGA PDF資料下載
參數(shù)資料
| 型號： | AD1556 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 24-Bit ADC WITH LOW NOISE PGA |
| 中文描述： | 24位ADC與低噪聲PGA巡回 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 429K |
| 代理商： | AD1556 |
REV. B
–5–
AD1555/AD1556
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Unit
CLKIN Frequency
1
CLKIN Duty Cycle Error
MCLK Output Frequency
1
f
CLKIN
0.975
45
1.024
1.075
55
MHz
%
f
CLKIN
/4
SYNC Setup Time
SYNC Hold Time
CLKIN Rising to MCLK Output Falling on SYNC
CLKIN Falling to MCLK Output Rising
CLKIN Falling to MCLK Output Falling
MCLK Input Falling to MDATA Falling
MCLK Input Rising to MDATA and MFLG Valid
TDATA Setup Time after SYNC
TDATA Hold Time
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
t
30
t
31
t
32
t
33
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
20
30
100
5
5
RESET Setup Time
RESET Hold Time
15
15
ns
ns
CLKIN Falling to DRDY Rising
CLKIN Rising to DRDY Falling
2
CLKIN Rising to
ERROR
Falling
20
20
50
ns
ns
ns
RSEL to Data Valid
RSEL Setup to SCLK Falling
DRDY to Data Valid
DRDY High Setup to SCLK Falling
R/
W
to Data Valid
R/
W
High Setup to SCLK Falling
CS
to Data Valid
CS
Low Setup to SCLK Falling
SCLK Rising to DOUT Valid
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Period
SCLK Falling to DRDY Falling
2
CS
High or R/
W
Low to DOUT Hi-Z
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
25
10
25
10
25
10
25
25
25
70
20
20
R/
W
Low Setup to SCLK Falling
CS
Low Setup to SCLK Falling
Data Setup Time to SCLK Falling
Data Hold Time after SCLK Falling
R/
W
Hold Time after SCLK Falling
10
10
10
10
10
ns
ns
ns
ns
ns
NOTES
1
The gain of the modulator is proportional to f
and MCLK frequency.
2
With DRDYBUF low only. When DRDYBUF is high, this timing also depends on the value of the external pull-down resistor.
Specifications subject to change without notice.
(+V
A
= +5 V 5%; –V
A
= –5 V 5%; AD1555 V
L
= 5 V
5%, AD1556 V
L
= 2.85 V to 5.25 V;
CLKIN = 1.024 MHz; AGND = DGND = 0 V; C
L
= 50 pF; T
A
= T
MIN
to T
MAX
, unless otherwise noted)
I
OH
I
OL
TO OUTPUT
PIN
1.4V
C
L
50pF
500 A
1.6mA
Figure 2. Load Circuit for Digital Interface Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD15700 | 1 MSPS 16-/14-Bit Analog I/O Port |
| AD15700BCA | 1 MSPS 16-/14-Bit Analog I/O Port |
| AD1580A | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD1580ART | 1.2 V Micropower, Precision Shunt Voltage Reference |
| AD1580ART-REEL1 | 1.2 V Micropower, Precision Shunt Voltage Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1556AS | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 256ksps 24-bit Parallel/Serial 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1556ASRL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 256ksps 24-bit Parallel/Serial 44-Pin MQFP T/R |
| AD1556ASZ | 功能描述:IC ADC PGA 24BIT LN 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD1556ASZRL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 256ksps 24-bit Parallel/Serial 44-Pin MQFP T/R |
| AD-155A | 功能描述:線性和開關(guān)式電源 51.55W 13.8V/10.5A 13.3V/0.5A RoHS:否 制造商:TDK-Lambda 產(chǎn)品:Switching Supplies 開放式框架/封閉式:Enclosed 輸出功率額定值:800 W 輸入電壓:85 VAC to 265 VAC 輸出端數(shù)量:1 輸出電壓（通道 1）:20 V 輸出電流（通道 1）:40 A 商用/醫(yī)用: 輸出電壓（通道 2）: 輸出電流（通道 2）: 安裝風(fēng)格:Rack 長度: 寬度: 高度: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。