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參數(shù)資料
| 型號： | AD1385TD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit 500 kHz Wide Temperature Range Sampling ADC |
| 中文描述： | 1-CH 16-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP48 |
| 封裝： | BOTTOM BRAZED, CERAMIC, DIP-48 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 348K |
| 代理商： | AD1385TD |
AD1385
REV. 0
–7–
Figure 13. AD1385 Functional Block Diagram
T HE ORY OF OPE RAT ION
T he AD1385 performs conversions using a three-pass subrang-
ing technique. T his proven circuit concept, implemented with
state of the art components, allows the ADC, track-hold, and a
low noise reference to fit into a single hermetic package, simpli-
fying the task of board design. T he T /H and ADC portions of
the AD1385 are distinct circuits with inputs and outputs avail-
able on separate pins. T his functional division allows greatest
application flexibility. T he AD1385’s major functional blocks
are shown in Figure 13.
T he T /H uses a low noise high performance hybrid amplifier and
high speed analog switches to achieve precision performance. It
operates as an inverting amplifier during T rack mode. Summing
junction switch S1 disconnects the analog input to place the cir-
cuit into Hold mode; the amplifier’s output stays constant because
the dc path to its inverting input is broken. S1 also grounds the
junction of R1 and R2 to minimize signal feedthrough. Pedestal
is independent of the analog input level because all switching
is done near ground. T his ensures very low nonlinearity and
distortion.
A precision Reference DAC and an 8-bit flash ADC form the
heart of the AD1385’s subranging design. High speed amplifiers
combine the analog input and DAC output to produce the volt-
ages encoded by the flash ADC during each pass. A logic array
provides all necessary timing, control, and computation.
T he first rising clock edge after Start Convert goes high begins
the conversion (provided the previous conversion is complete).
T he Hold Command goes high and switches the T /H into hold.
T he held signal from the T /H goes through S2, S3, and Error
Amp 2 to the flash ADC. During this pass Error Amp 2 actually
attenuates the ADC input to keep the voltage within the flash
ADC’s input range. T he flash ADC is strobed after a 100 ns
settling period. T he 8-bit result is saved in the logic array and is
routed to the MSBs of the Reference DAC.
Error Amp 1 amplifies the difference between the Reference
DAC output and the held input signal during the second pass.
S4 routes this error signal to the flash ADC, which is strobed a
second time after Error Amp 1 has settled. T he new 8-bit result
is used to correct the previous result, increasing the accuracy of
this intermediate answer to 13-bit precision. Following this the
Reference DAC is updated.
Both error amplifiers are active during the third pass. S2 is
closed, allowing Error Amp 2 to amplify Error Amp 1’s output.
S3 now brings Error Amp 2’s output to the flash ADC. T he
flash ADC is strobed a final time after the DAC and both error
amplifiers have settled. T he logic array combines the data from
the third flash conversion with the earlier 13-bit word to pro-
duce the final 16-bit result. T he T /H is returned to track mode,
and Error Amp 2 is reconnected as an attenuator 50 ns after the
completion of the third flash conversion to prepare for the next
conversion.
T he output data are placed on the data bus in two 8-bit bytes
to be read by the host system. T he Data Strobe output synchro-
nizes the data transfer by providing a rising edge for the first
byte and a falling edge for the second byte. T he Hi/Lo Byte
Select input allows the user to choose which data byte is pre-
sented first. B1 Select sets the polarity of the MSB to provide
either complementary twos complement or complementary off-
set binary data.
T he AD1385’s internal linearity calibration capability may be
used to compensate for shifts in Reference DAC linearity with
time and temperature. T he calibration sequence uses the
AD1385’s error amplifiers and flash converter to directly mea-
sure Reference DAC linearity errors. T he routine calculates the
Corrections required to each of the Reference DAC’s 8 MSBs
and stores these in an internal memory; the memory address is
determined by the Reference DAC’s codes. T he RAM data con-
trol a Correction DAC whose output is summed with the Refer-
ence DAC’s output. T ogether the two DACs provide the 18-bit
linearity required for accurate A/D conversions. Calibration
corrects only linearity errors, and has a negligible effect on
gain and offset errors. A calibration cycle requires 15 ms and
may be initiated at any time (see Autozero).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD1385TD/883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit 500 kHz Wide Temperature Range Sampling ADC |
| AD-1386 | 功能描述:烙鐵 CALIBRATION GUAGE RoHS:否 制造商:Weller 產品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included |
| AD-1386-CALIBRATION-GA | 制造商:TE Connectivity 功能描述:AD-1386-CALIBRATION-GAUGE 992013-000 |
| AD-1386-CALIBRATION-GAUGE | 功能描述:手工工具 AD-1386-CALIBRATION-GAUGE RoHS:否 制造商:Molex 產品:Extraction Tools 類型: 描述/功能:Extraction tool |
| AD1386-CALIBRATION-GAUGE | 制造商:TE Connectivity 功能描述:AD-1386-CALIBRATION-GAUGE |
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