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參數(shù)資料
| 型號(hào)： | AD1377KD |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC SNGL 16BIT 32-CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 111k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-DIP（0.900"，22.86mm） |
| 供應(yīng)商設(shè)備封裝： | 32-BBDIP-H |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 16 個(gè)單端，雙極；16 個(gè)單端，單極 |
AD1376/AD1377
Rev. D | Page 10 of 12
HIGH RESOLUTION DATA ACQUISITION SYSTEM
The essential details of a high resolution data acquisition system
using a 16-bit sample-and-hold amplifier (SHA) and the
AD1376/AD1377 are shown in Figure 14. Conversion is
initiated by the falling edge of the CONVERT START pulse.
This edge drives the device’s STATUS line high. The inverter
then drives the SHA into hold mode. STATUS remains high
throughout the conversion and returns low once the conversion
is completed. This allows the SHA to re-enter track mode.
This circuit can exhibit nonlinearities arising from transients
produced at the ADC’s input by the falling edge of CONVERT
START. This edge resets the ADC’s internal DAC; the resulting
transient depends on the SHA’s present output voltage and the
ADC’s prior conversion result. In the circuit of Figure 15, the
falling edge of CONVERT START also places the SHA into hold
mode (via the ADC’s STATUS output), causing the reset
transient to occur at the same moment as the SHA’s track-and-
hold transition. Timing skews and capacitive coupling can cause
some of the transient signal to add to the signal being acquired
by the SHA, introducing nonlinearity.
00
69
9-
01
4
SHA
AD1376/
AD1377
30
21
28
22
24
27
26
19
18
31
BITS
1–16
+
CONVERT
START
–10V TO +10V
+
10
F
+
10
F
10
F
+15V
–15V
+5V
ANALOG
INPUT
–10V TO +10V
Figure 14. Basic Data Acquisition System Interconnections 16-Bit SHA
A much safer approach is to add a flip-flop, as shown in
Figure 15. The rising edge of CONVERT START places the
track-and-hold device into hold mode before the ADC reset
transients begin. The falling edge of STATUS places the SHA
back into track mode. System throughput will be reduced if a
long CONVERT START pulse is used. Throughput can be
calculated from
CS
CONV
ACQ
T
Throughput
+
=
1
where:
TACQ is the track-and-hold acquisition time.
TCONV is the time required for the ADC conversion.
TCS is the duration of CONVERT START.
The combination of the AD1376 and a 16-bit SHA can provide
greater than 50 kHz throughput. No significant track-and-hold
droop error will be introduced, provided the width of
CONVERT START is small compared with the ADC’s
conversion time.
0
06
99
-0
15
SHA
AD1376/
AD1377
30
21
28
22
24
27
26
19
18
31
BITS
1–16
+
–10V TO +10V
+
10
F
+
10
F
10
F
+15V
–15V
+5V
ANALOG
INPUT
–10V TO +10V
CONVERT
START
HC112
S
R
Q
J
Q
K
+5V
Figure 15. Improved Data Acquisition System
1
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