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參數(shù)資料
| 型號(hào)： | AD10678BWS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | CLAMP |
| 中文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, XMA120 |
| 封裝： | 2.200 X 2.800 INCH, SURFACE MOUNT MODULE |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 673K |
| 代理商： | AD10678BWS |
AD10678
THEORY OF OPERATION
The AD10678 employs four parallel, high speed analog-to-digital
converters in a correlation technique to improve the dynamic
range of the ADCs. The technique consists of summing the
parallel outputs of the four converters to reduce the uncorrelated
noise introduced by the individual converters. Signals processed
through the high speed adder are correlated and summed
coherently. Noise is not correlated and sums on an rms basis.
Rev. A | Page 13 of 20
The four high speed, analog-to-digital converters employ a three-
stage subrange architecture. The AD10678 provides
complementary analog input pins, AIN and
AIN
. Each analog
input is centered around 2.4 V and should swing ±0.55 V around
the reference. Since AIN and
AIN
are 180 degrees out of phase,
the differential analog input signal is 2.15 V p-p.
The analog input is designed for a 50 input impedance for easy
interface to commercially available cables, filters, and drivers, etc.
The AD10678 encode inputs are ac-coupled to a PECL differential
receiver/driver. The output of the receiver/driver provides a clock
source for a 1:5 PECL clock driver and a PECL-to-TTL translator.
The 1:5 PECL clock driver provides the differential encode signal
for each of the four high speed analog-to-digital converters. The
PECL-to-TTL translator is used to provide a clock source for the
complex programmable logic device (CPLD).
The digital outputs from the four ADCs drive 120 series output
terminators and are applied to the CPLD for postprocessing. The
digital outputs are added together in the complex programmable
logic device through a ripple-carry adder, which provides the
16-bit data output. The AD10678 provides valid data following
10 pipeline delays. The result is a 16-bit parallel digital CMOS
compatible word coded as true binary.
Input Stage
The user is provided with a single-to-differential transformer
coupled input. The input impedance is 50 and requires a
2.15 V p-p input level to achieve full scale.
Encoding the AD10678
The AD10678 encode signal must be a high quality, low phase
noise source to prevent performance degradation. The clock input
must be treated as an analog input signal because aperture jitter
may affect dynamic performance. For optimum performance, the
AD10678 must be clocked differentially.
Output Loading
Take care when designing the data receivers for the AD10678. The
complex programmable logic device 16-bit outputs drive 120
series resistors to limit the amount of current that can flow into
the output stage. To minimize capacitive loading, there should
only be one gate on each of the output pins. A typical CMOS gate
combined with the PCB trace has a load of approximately 10 pF. It
should be noted that extra capacitive loading increases output
timing and invalidates timing specifications. Digital output timing
is guaranteed with a 10 pF load.
and Digital Power Supplies
Analog
Care must be taken when selecting a pow
supplies are recommended. Switching supplies tend to have
radiated components that may be coupled into the ADCs. Th
AD10678 features separate analog and digital supply and
ground currents, helping to minimize digital corruption of
sensitive analog signals.
er source. Linear
e
ower to the clock distribution
ut
he
nts
e
.
arate analog and digital
, high
s
ize
78
The +3.3VE supply provides p
circuit. The +3.3VD supply provides power to the digital outp
section of the ADCs, the PECL-to-TTL translator, and the
CPLD. Separate +3.3VE and +3.3VD supplies are used to
prevent modulation of the clock signal with digital noise. T
+5VA supply provides power to the analog sections of the
ADCs. Decoupling capacitors are strategically placed
throughout the circuit to provide low impedance noise shu
to ground. The +5VA supply (analog power) should be
decoupled to AGND (analog ground) and +3.3VD (digital
power) should be decoupled to DGND (digital ground). Th
+3.3VE supply (analog power) should be decoupled to AGND
The evaluation board schematic and layout data provide a
typical PCB implementation of the AD10678.
Analog and Digital Grounding
Although the AD10678 provides sep
ground pins, the device should be treated as an analog
component. Proper grounding is essential in high speed
resolution systems. Multilayer printed circuit boards are
recommended to provide optimal grounding and power
distribution. The use of power and ground planes provide
distinct advantages. Power and ground planes minimize the
loop area encompassed by a signal and its return path, minim
the impedance associated with power and ground paths, and
provide a distributed capacitor formed by the power plane,
printed circuit board material, and ground plane. The AD106
unit is provided with four metal standoffs (see Figure 7). MH2
is located in the center of the unit and MH1 is located directly
below analog header P3. Both of these standoffs are tied to
analog ground and should be connected accordingly on the
next level assembly for optimum performance. The two
standoffs located near P1 and P2 (MH3 and MH4) are tied to
digital ground and should be connected accordingly on the
next-level assembly.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD1072-12F | 制造商:MPD 制造商全稱:MicroPower Direct, LLC 功能描述:Very Low Cost, 72W DIN Rail Mount Single Output AC/DC Power Supplies |
| AD1072-24F | 制造商:MPD 制造商全稱:MicroPower Direct, LLC 功能描述:Very Low Cost, 72W DIN Rail Mount Single Output AC/DC Power Supplies |
| AD1072-48F | 制造商:MPD 制造商全稱:MicroPower Direct, LLC 功能描述:Very Low Cost, 72W DIN Rail Mount Single Output AC/DC Power Supplies |
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