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參數(shù)資料
| 型號： | AD10465BZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL 14BIT 68-CLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 3.9W |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-CLCC |
| 供應(yīng)商設(shè)備封裝： | 68-CLCC（24.13x24.13） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 6 個單端，雙極 |
AD10465
Rev. A | Page 14 of 24
POWER SUPPLIES
Care should be taken when selecting a power source. Linear
supplies are strongly recommended. Switching supplies tend to
have radiated components that can be “received” by the
AD10465. Each of the power supply pins should be decoupled
as closely to the package as possible using 0.1 μF chip
capacitors.
The AD10465 has separate digital and analog power supply
pins. The analog supplies are denoted AVCC and the digital
supply pins are denoted DVCC. AVCC and DVCC should be
separate power supplies. This is because the fast digital output
swings can couple switching current back into the analog sup-
plies. Note that AVCC must be held within 5% of 5 V. The
AD10465 is specified for DVCC = 3.3 V as this is a common
supply for digital ASICs.
OUTPUT LOADING
Care must be taken when designing the data receivers for the
AD10465. The digital outputs drive an internal series resistor (for
example, 100 Ω) followed by a gate, such as the 75LCX574. To
minimize capacitive loading, there should only be one gate on each
output pin. An example of this is shown in the evaluation board
schematic shown in Figure 26. The digital outputs of the AD10465
have a constant output slew rate of 1 V/ns. A typical CMOS gate
combined with a PCB trace has a load of approximately 10 pF.
Therefore, as each bit switches, 10 mA (10 pF × 1 V ÷1 ns) of
dynamic current per bit flows in or out of the device. A full-scale
transition can cause up to 140 mA (14 bits ×10 mA/bit) of current
flow through the output stages. These switching currents are
confined between ground and the DVCC pin. Standard TTL gates
should be avoided because they can appreciably add to the dynamic
switching currents of the AD10465. It should also be noted that
extra capacitive loading increases output timing and invalidates
timing specifications. Digital output timing is guaranteed with
10 pF loads.
LAYOUT INFORMATION
The schematic of the evaluation board (see Figure 24)
represents a typical implementation of the AD10465. The
pinout of the AD10465 is very straightforward and facilitates
ease of use and the implementation of high frequency/high
resolution design practices. It is recommended that high quality
ceramic chip capacitors be used to decouple each supply pin to
ground directly at the device. All capacitors can be standard
high quality ceramic chip capacitors.
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the ADC through a resistor network to eliminate
the need to externally isolate the device from the receiving gate.
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| AD10465PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Channel, 14-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning |
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| AD1048-24FS | 制造商:MPD 制造商全稱:MicroPower Direct, LLC 功能描述:Very Low Cost, 36 - 48W DIN Rail Mount Single Output AC/DC Power Supplies |
| AD1048-48FS | 制造商:MPD 制造商全稱:MicroPower Direct, LLC 功能描述:Very Low Cost, 36 - 48W DIN Rail Mount Single Output AC/DC Power Supplies |
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