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參數(shù)資料
| 型號： | AD10242BZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL 12BIT 68-CLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 2W |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-CLCC |
| 供應(yīng)商設(shè)備封裝： | 68-CLCC（24.13x24.13） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 6 個單端，雙極 |
| 配用： | AD10242/PCB-ND - KIT EVAL PCB FOR AD10242 |
Test
Mil
AD10242BZ/TZ
Parameter
Temp
Level
Subgroup
Min
Typ
Max
Unit
SPURIOUS-FREE DYNAMIC RANGE
9
Analog Input @ 1.2 MHz
25
°CI
81
dBFS
@ 4.85 MHz
25
°CI
47080
dBFS
Full
II
5, 6
70
79
dBFS
@ 9.9 MHz
25
°CI
46370
dBFS
Full
II
5, 6
63
69
dBFS
@ 19.5 MHz
25
°CI
46067
dBFS
Full
II
5, 6
60
66
dBFS
TWO-TONE IMD REJECTION
10
F1, F2 @ –7 dBFS
Full
II
4, 5, 6
70
76
dBc
CHANNEL-TO-CHANNEL ISOLATION
11
25
°CIV
12
75
80
dB
TRANSIENT RESPONSE
25
°CV
10
ns
LINEARITY
Differential Nonlinearity
25
°CIV
12
0.3
1.0
LSB
(Encode = 20 MHz)
Full
IV
12
0.5
1.25
LSB
Integral Nonlinearity
25
°CV
0.3
LSB
(Encode = 20 MHz)
Full
V
0.5
LSB
OVERVOLTAGE RECOVERY TIME
12
VIN = 2.0
× FS
Full
IV
12
50
100
ns
VIN = 4.0
× FS
Full
IV
12
75
200
ns
DIGITAL OUTPUTS
Logic Compatibility
CMOS
Logic “1” Voltage
13
Full
I
1, 2, 3
3.5
4.2
V
Logic “0” Voltage
14
Full
I
1, 2, 3
0.45
0.65
V
Output Coding
Twos Complement
POWER SUPPLY
AVCC Supply Voltage
Full
VI
5.0
V
I (AVCC) Current
Full
V
260
mA
AVEE Supply Voltage
Full
VI
–5.0
V
I (AVEE) Current
Full
V
55
mA
DVCC Supply Voltage
Full
VI
5.0
V
I (DVCC) Current
Full
V
25
mA
ICC (Total) Supply Current
Full
I
1, 2, 3
350
400
mA
Power Dissipation (Total)
Full
I
1, 2, 3
1.75
2.0
W
Power Supply Rejection Ratio (PSRR)
Full
I
7, 8
0.01
0.02
% FSR/% VS
Pass-Band Ripple to 10 MHz
Full
IV
12
0.2
dB
NOTES
1Gain tests are performed on A
IN3 over specified input voltage range.
2Input capacitance specifications combine AD9632 die capacitance and ceramic package capacitance.
3Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4ENCODE driven by single-ended source;
ENCODE bypassed to ground through 0.01
F capacitor.
5ENCODE may also be driven differentially in conjunction with
ENCODE; see Encoding the AD10242 section for details.
6Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50%
± 5%.
7Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 40.0 MSPS.
8Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 40.0 MSPS.
9Analog Input signal equals –1 dBFS; SFDR is the ratio of converter full scale to worst spur.
10Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = 10.0 MHz
± 100 kHz, 50 kHz ≤ f1 – f2 ≤ 300 kHz.
11Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel (A
IN1).
12Input driven to 2
× and 4× A
IN1 range for >4 clock cycles. Output recovers in band in specified time with Encode = 40 MSPS. No foldover guaranteed.
13Outputs are sourcing 10
A.
14Outputs are sinking 10
A.
All specifications guaranteed within 100 ms of initial power-up regardless of sequencing.
Specifications subject to change without notice.
AD10242
–3–
REV. C
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