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參數(shù)資料
| 型號(hào)： | ACTX1018S-FREQ-E25-H5-OUT2 |
| 廠商： | ABRACON CORP |
| 元件分類： | TCXO, sine |
| 英文描述： | TCXO, CLIPPED SINE OUTPUT, 8 MHz - 45 MHz |
| 封裝： | COMPACT, DIP-4 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 177K |
| 代理商： | ACTX1018S-FREQ-E25-H5-OUT2 |
29 Journey Aliso Viejo, CA 92656 USA
(949) 448-7070
FAX: (949) 448-8484
E-MAIL:
abinfo @ abracon.com INTERNET ADDRESS: www.abracon.com
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
CORPORA TION
ABRACON
-57 -
CRYSTAL OSCILLATORS
APPLICATION NOTES
CMOS RISE AND FALL TIMES
The rise and fall time on the CMOS technology depends on its
speed (CMOS, HCMOS, ACMOS, BICMOS), the supply voltage,
the load capacitance, and the load configuration. Typical rise and
fall time for CMOS 4000 series is 30ns, HCMOS is 6ns, and for
ACMOS (HCMOS, TTL compatible) is 3 ns max.
Typical rise and fall
time
is
measured
between 10% to 90%
of its waveform level.
(See example of
Wave Output; Fig. 1.)
ACMOS OUTPUT TERMINATION TECHNIQUES
Due to the fast transition time of the ACMOS (HCMOS/TTL com-
patible) device, proper termination techniques must be used
when testing or measuring electrical performance characteris-
tics.
Termination is usually used to solve the problem of voltage
reflection, which essential cause steps in clock waveforms as
well as overshoot and undershoot. Such effect could result in
false clocking of data, as well as higher EMI and system noise.
Termination is required also because of the length of the trace on
the PC board and its load configuration.
There are three general methods of terminating a clock trace,
which is a process of matching the output impedance of the
device with the line impedance:
1) Series termination;
2) Pull-up/Pull-down termination;
3) Parallel-AC termination
METHOD 1:
Series termination (Fig. 3)
In series termination, a damping resistor is placed close to the
source of the clock signal. Value of Rs must satisfy the following
requirement:
METHOD 2 :
Pull-Up / Pull-Down Resistors (Fig. 4)
Figure 4
In pull-up/pull-down termination, the Thevenin’s equivalent of the
combination is equal to the characteristics impedance of the
trace. This is probably the cleanest, and results in no reflections,
as well as EMI.
RT ~ ZT
METHOD 3 :
Parallel AC Termination (Fig. 5)
Figure 5
In parallel AC termination, a R-C combination is placed at the
load. The value of the capacitor must be chosen carefully, usual-
ly smaller than the 50pF. This termination is not recommended
because it will degrade the rise and fall time of the clock, al-
though it draws no DC current.
OUTPUT
WAVEFORM
Figure 1
Figure 3
Rs >
_ ZT - Ro
DUT
R1
R2
Vcc
ZT
LOAD
DUT
RS
ZT
LOAD
DUT
RL
CL
Cc
ZT
VoH
VoL
Overshoot
Undershoot
Figure 2
22355 Abracon CORX 2-29.qxd
3/6/00
6:55 AM
Page 57
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACVTX1018-FREQ-F25-H5-OUT23 | TCVCXO, CLOCK, 1 MHz - 26 MHz, CMOS/TTL OUTPUT |
| ACVTX1018-FREQ-E50-H5-OUT23 | TCVCXO, CLOCK, 1 MHz - 26 MHz, CMOS/TTL OUTPUT |
| ACVTX1018SA-FREQ-C30-H5-OUT1 | TCVCXO, SINE OUTPUT, 8 MHz - 45 MHz |
| ACVTX1018SA-FREQ-F25-H5-OUT1 | TCVCXO, SINE OUTPUT, 8 MHz - 45 MHz |
| ACVTX1018S-FREQ-C30-H5-OUT2 | TCVCXO, CLIPPED SINE OUTPUT, 8 MHz - 45 MHz |
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