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參數(shù)資料
| 型號： | ACT-S2M32A-120F18M |
| 廠商： | Aeroflex Inc. |
| 英文描述： | 8-Line To 1-Line Data Selectors/Multiplexers 16-SOIC 0 to 70 |
| 中文描述： | 行為F2M32A高速64兆扇區(qū)擦除閃存多芯片模塊 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 92K |
| 代理商： | ACT-S2M32A-120F18M |
Aeroflex Circuit Technology
SCD1666A REV A 9/12/97 Plainview NY (516) 694-6700
4
AC Characteristics – Write/Erase/Program Operations – WE Controlled
(T
C
= -55
°
C to +125
°
C, V
CC
= +4.5V to + 5.5V, Unless otherwise specified)
Parameter
Parameter
Symbol
Standard
t
WC
Parameter
Symbol
JEDEC
t
AVAV
90ns
120ns
150ns
Units
Min
Max
Min
Max
Min
Max
Write Cycle Time
90
120
150
ns
Address Setup to WE Going Low
t
AS
t
AVWL
0
0
0
ns
Address Hold Time from CE High
t
AH
t
WLAX
45
50
50
ns
Data Setup to WE Going High
t
DS
t
DVWH
45
50
50
ns
Data Hold Time from WE High
t
DH
t
WHDX
0
0
0
0
10
0
0
ns
ns
ns
Output Enable Hold Time
Read
t
OEH
Toggle Bit I and Data Polling
10
10
Read Recover Time Before Write
(OE High to WE Low)
t
GHWL
t
GHWL
0
0
0
ns
CE Setup Time from WE Low
t
CS
t
ELWL
0
0
0
ns
CE Hold Time from WE High
t
CH
t
WHEH
0
0
0
ns
WE Pulse Width
t
WP
t
WLWH
45
50
50
ns
WE Pulse Width High
t
WPH
t
WHWL
20
20
20
ns
Byte Programming Operation
t
WHWH
1
t
WHWH
1
8
8
8
μs
Sector Erase Operation
t
WHWH
2
t
WHWH
2
15
15
15
Sec
V
CC
Set-Up Time
t
VCS
50
50
50
μs
Rise Time to V
ID
t
VIDR
t
OESP
t
RP
500
500
500
ns
OE Setup Time to WE Active
4
4
4
μs
Reset Pulse Width
500
500
500
ns
Program/Erase Valid to RY/BY
Delay
Notes:
1. Not 100% tested.
t
BUSY
40
50
60
ns
AC Characteristics – Read Only Operations
(T
C
= -55
°
C to +125
°
C, V
CC
= +4.5V to + 5.5V, Unless otherwise specified)
Parameter
Parameter
Symbol
Standard
t
RC
Parameter
Symbol
JEDEC
t
AVAV
90ns
120ns
150ns
Units
Min Max
Min Max
Min Max
Read Cycle Time
(1)
90
120
150
ns
Address to Output Delay
t
ACC
t
AVQV
90
120
150
ns
CE to Output Delay
t
CE
t
ELQV
90
120
150
ns
OE to Output Delay
t
OE
t
GLQV
40
50
55
ns
CE to Output in High Z
(1)
t
DF
t
EHQZ
20
30
35
ns
OE to Output in High Z
(1)
t
DF
t
GHQZ
20
0
30
0
35
ns
Output Hold from Addresses, CE or OE Change, Whichever Occurs
First
t
OH
t
AXQX
0
0
0
ns
RESET Low to Read Mode
(1)
Notes:
1. Not 100% tested.
t
READY
20
20
20
μs
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