參數(shù)資料
型號: ACT-D1M96S-020F20Q
廠商: Aeroflex Inc.
英文描述: ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module
中文描述: 行為D1M96S高速96兆位同步DRAM 3.3V的多芯片模塊
文件頁數(shù): 6/14頁
文件大?。?/td> 105K
代理商: ACT-D1M96S-020F20Q
Aeroflex Circuit Technology
SCD3369-1 REV C 5/31/00 Plainview NY (516) 694-6700
6
Table 1 — Basic Command Truth
Table
Command
State of
Bank(s)
CS1
CS2
RAS1
RAS2
CAS1
CAS2
WE1
WE2
A11
BA11
A10
BA10
A9-A0
BA9-BA0
Mne-
monic
Mode register set
T = deac
B = deac
L
L
L
L
X
X
A9,BA9 = V
A8,BA8,A7,BA7 = 0
A6-A0,BA6-BA0 = V
MRS
Bank deactivate (precharge)
X
L
L
H
L
BS
L
X
DEAC
Deactivate all banks (precharge)
X
L
L
H
L
X
H
X
DCAB
Bank activate/row-address entry
SB = deac
L
L
H
H
BS
V
V
ACTV
Column-address entry/write
operation
SB = actv
L
H
L
L
BS
L
V
WRT
Column-address entry/write
operation with auto-deactivate
SB = actv
L
H
L
L
BS
H
V
WRT-P
Column-address entry/read
operation
SB = actv
L
H
L
H
BS
L
V
READ
Column-address entry/read
operation with auto-deactivate
SB = actv
L
H
L
H
BS
H
V
READ-P
Burst stop
SB = actv
L
H
H
L
X
X
X
STOP
No operation
X
L
H
H
H
X
X
X
NOOP
Control-input inhibit/no operation
X
H
X
X
X
X
X
X
DESL
Auto refresh
§
T = deac
B = deac
L
L
L
H
X
X
X
REFR
NOTES
:
For execution of these commands on cycle n:
-CKE (n-1) must be high, or
-tCES and nCLE must be satisfied for clock-suspend exit.
DQMx(n) is a don’t care.
All other unlisted commands are considered vendor-reserved commands or illegal commands.
§ Auto-refresh entry requires that all banks be deactivated or in an idle state prior to the command entry.
Legend:
n = CLK cycle number, L = Logic low, H = Logic high, X = Don’t care, either logic low or logic high, V = Valid, T = Bank T, B = Bank B, actv = Activated, deac = Deactivated, BS
= Logic high to select bank T; logic low to select bank B, SB = Bank selected by A11 at cycle n
Table 2 — Clock Enable (CKE) Command Truth Table
Command
State of Bank(s)
CKE
(n-1)
CKE
(n)
CS
(n)
RAS
(n)
CAS
(n)
WE
(n)
Mnemonic
CLK suspend on cycle (n + 1)
T = access operation
B = access operation
H
L
X
X
X
X
HOLD
CLK suspend exit on cycle (n + 1)
T = access operation
B = access operation
L
H
X
X
X
X
NOTES
:
For execution of these commands, A0-A11 (n) and DQMx (n) are don’t cares.
All other unlisted commands are considered vendor-reserved commands or illegal commands.
A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write operation.
Legend:
n = CLK cycle number, L = Logic low, H = Logic high, X = Don’t care, either logic low or logic high, T = Bank T, B = Bank B
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