參數(shù)資料
型號(hào): ACT-9S512K8N-012L2T
廠商: Aeroflex Inc.
英文描述: ACT-PS512K8 High Speed 4 Megabit Plastic Monolithic SRAM
中文描述: 行為PS512K8高速4兆位單片SRAM的塑料
文件頁(yè)數(shù): 4/6頁(yè)
文件大小: 73K
代理商: ACT-9S512K8N-012L2T
Aeroflex Circuit Technology
SCD3764 REV A 6/2/98 Plainview NY (516) 694-6700
4
Timing Diagrams — SRAM
D
I/O
t
RC
t
OH
t
AA
Data Valid
Previous Data Valid
t
OE
High Z
t
OHZ
Read Cycle Timing Diagrams
Data Valid
t
CLZ
SCE
OE
t
ACE
t
CHZ
UNDEFINED
DON’T CARE
Read Cycle 2 (SWE = V
IH
)
Write Cycle (SCE Controlled, OE = V
IH
)
t
CW
t
AS
t
WP
t
DW
t
OW
t
DH
SCE
SWE
Data Valid
Write Cycle (SWE Controlled, OE = V
IH
)
D
I/O
AC Test Circuit
I
OL
Parameter
Typical
Units
Input Pulse Level
0 – 3.0
V
Input Rise and Fall
5
ns
Input and Output Timing Reference Level
1.5
V
Notes:
1) V
Z
is programmable from -2V to +7V. 2) I
OL
and I
OH
programmable from 0 to 16 mA. 3) Tester Impedance
Z
O
= 75
. 4)
V
Z
is typically the midpoint of V
OH
and V
OL
. 5) I
OL
and I
OH
are adjusted to simulate a typical resistance
load circuit. 6) ATE Tester includes jig capacitance.
I
OH
To Device Under Test
V
Z
~ 1.5 V (Bipolar Supply)
Current Source
Current Source
C
L
= 50 pF
t
WC
t
AW
t
AH
t
RC
t
AA
t
OLZ
S
EE
OTE
S
EE
N
OTE
S
EE
OTE
S
EE
N
OTE
Note: Guaranteed by design, but not tested.
D
I/O
t
OTE
S
EE
N
Read Cycle 1 (SCE = OE = V
IL
, SWE = V
IH
)
Write Cycle Timing Diagrams
t
WP
t
DW
Data Valid
t
WC
t
AW
t
AH
D
I/O
t
DH
SCE
SWE
t
CW
t
AS
A
0-18
A
0-18
A
0-18
A
0-18
AC Test Conditions
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