- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362070 > ACT-700SC-250F17C Microprocessor PDF資料下載
參數(shù)資料
| 型號(hào)： | ACT-700SC-250F17C |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 227K |
| 代理商： | ACT-700SC-250F17C |
Aeroflex Circuit Technology
SCD7000 REV A 3/16/00 Plainview NY (516) 694-6700
20
Pin Descriptions
The following is a list of control, data, clock, interrupt, and miscellaneous pins of the ACT 7000SC.
Pin Name
Type
Description
System interface:
ExtRqst*
Input
External request
Signals that the system interface is submitting an external request.
Release*
Output
Release interface
Signals that the processor is releasing the system interface to slave state
RdRdy*
Input
Read Ready
Signals that an external agent can now accept a processor read.
WrRdy*
Input
Write Ready
Signals that an external agent can now accept a processor write request.
ValidIn*
Input
Valid Input
Signals that an external agent is now driving a valid address or data on the
SysAD bus and a valid command or data identifier on the SysCmd bus.
ValidOut*
Output
Valid output
Signals that the processor is now driving a valid address or data on the SysAD
bus and a valid command or data identifier on the SysCmd bus.
SysAD(63:0)
Input/
Output
System address/data bus
A 64-bit address and data bus for communication between the processor and an
external agent.
SysADC(7:0)
Input/
Output
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data cycles.
SysCmd(8:0)
Input/
Output
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor
and an external agent.
SysCmdP
Input/
Output
System Command/Data Identifier Bus Parity
For the RM7000, unused on input and zero on output.
Clock/Control interface:
SysClock
Input
System clock
Master clock input used as the system interface reference clock. All output
timings are relative to this input clock. Pipeline operation frequency is derived by
multiplying this clock up by the factor selected during boot initialization
VccP
Input
Vcc for PLL
Quiet VccInt for the internal phase locked loop. Must be connected to VccInt.
See Figure 10 for additional PPL filtering information.
VssP
Input
Vss for PLL
Quiet Vss for the internal phase locked loop. Must be connected to Vss.
See Figure 10 for additional PPL filtering information.
Interrupt Interface
Int*(5:0)
Input
Interrupt
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt
register.
NMI*
Input
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 15 of the interrupt register (bit 7 in R5000
compatibility mode).
Powered by ICminer.com Electronic-Library Service CopyRight 2003
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACT-700SC-250F17I | Microprocessor |
| ACT-700SC-250F17M | Microprocessor |
| ACT-700SC-250F17Q | Microprocessor |
| ACT-700SC-250F17T | Microprocessor |
| ACT-700SC-250F24C | Microprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACT-700SC-250F17I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| ACT-700SC-250F17M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| ACT-700SC-250F17Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| ACT-700SC-250F17T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| ACT-700SC-250F24C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。