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參數(shù)資料
| 型號(hào)： | ACS373D |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened Octal Transparent Latch, Three-State |
| 中文描述： | 輻射加固八路透明鎖存器，三態(tài) |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 91K |
| 代理商： | ACS373D |
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
ACS373MS
Radiation Hardened
Octal Transparent Latch, Three-State
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C
TOP VIEW
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
Q0
D0
D1
Q1
Q2
D3
D2
Q3
GND
VCC
D7
D6
Q6
Q7
Q5
D5
D4
Q4
LE
2
3
4
5
6
7
8
9
10
1
20
19
18
17
16
15
14
13
12
11
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
April 1995
Spec Number
518799
File Number
3999
Truth Table
OE
L
L
L
L
H
LE
H
H
L
L
X
D
H
L
I
h
X
Q
H
L
L
H
Z
NOTE:
L
= Low Voltage Level
H = High Voltage Level
I
= Low voltage level one set-up time prior to the high to low latch enable transition
h = High voltage level one set-up time prior to the high to low latch enable transition
X = Don’t Care
Z = High Impedance State
Functional Diagram
1 OF 8
(3, 4, 7, 8, 13,
14, 17, 18)
D
Q
LE
D
LE
(11)
Q
OE
(1)
LATCH
COMMON
CONTROLS
OE
(2, 5, 6, 9, 12,
15, 16, 19)
Ordering Information
PART NUMBER
ACS373DMSR
ACS373KMSR
ACS373D/Sample
ACS373K/Sample
ACS373HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
Features
1.25 Micron Radiation Hardened SOS CMOS
Total Dose 300K RAD (Si)
Single Event Upset (SEU) Immunity
<1 x 10
-10
Errors/Bit-Day (Typ)
SEU LET Threshold >80 MEV-cm
2
/mg
Dose Rate Upset >10
11
RAD (Si)/s, 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to ALSTTL Logic
DC Operating Voltage Range: 4.5V to 5.5V
Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
Input Current
≤
1
μ
A at VOL, VOH
Description
The Intersil ACS373MS is a radiation hardened octal transparent
latch with three-state outputs. The outputs are transparent to the
inputs when the latch enable (LE) is high. When the LE goes low,
the data is latched. When the Output Enable (OE) is high, the
outputs are in the high impedance state. The latch operation is
independent of the state of the output enable.
The ACS373MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACS373DMSR | Radiation Hardened Octal Transparent Latch, Three-State |
| ACS373HMSR | Radiation Hardened Octal Transparent Latch, Three-State |
| ACS373KMSR | Radiation Hardened Octal Transparent Latch, Three-State |
| ACS374D | Radiation Hardened Octal D Flip-Flop, Three-State |
| ACS374DMSR | Radiation Hardened Octal D Flip-Flop, Three-State |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACS373DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal Transparent Latch, Three-State |
| ACS373HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal Transparent Latch, Three-State |
| ACS373K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal Transparent Latch, Three-State |
| ACS373KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal Transparent Latch, Three-State |
| ACS373MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal Transparent Latch, Three-State |
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