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參數(shù)資料
| 型號： | ACS109D |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened Dual J-K Flip-Flop with Set and Reset |
| 中文描述： | 輻射硬化的設(shè)置和復(fù)位雙JK觸發(fā)器 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 39K |
| 代理商： | ACS109D |
1
File Number
4760
ACS109MS
Radiation Hardened Dual J-K Flip-Flop
with Set and Reset
The Radiation Hardened ACS109MS is a Dual J-K Flip-
Flop with Set and Reset. These Flip-Flops have
independent J, K, Set, Reset, and Clock inputs and Q and
Q outputs. The outputs change state on the positive-going
transition of the clock. Set and Reset are accomplished
asynchronously by Low-level inputs. All inputs are buffered
and the outputs are designed for balanced propagation
delay and transition times.
The ACS109MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS109MS are
contained in SMD 5962-98632. A “hot-link” is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/spaceselect.htm
Features
QML Qualified Per MIL-PRF-38535 Requirements
1.25 Micron Radiation Hardened SOS CMOS
Radiation Environment
- Latch-Up Free Under Any Conditions
- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 10
5
RAD(Si)
- SEU Immunity. . . . . . . . . . . . .<1 x 10
-10
Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm
2
)
Input Logic Levels. . . . V
IL
= (0.3)(V
CC
), V
IH
= (0.7)(V
CC
)
Output Current
. . . . . . . . . . . . . . . . . . . . . . . . . . ±
12mA (Min)
Quiescent Supply Current . . . . . . . . . . . . . . . 10
μ
A (Max)
Propagation Delay . . . . . . . . . . . . . . . . . . . . . .25ns (Max)
Applications
High Speed Control Circuits
Sensor Monitoring
Low Power Designs
Ordering Information
ORDERING NUMBER
INTERNAL MARKETING
NUMBER
TEMP. RANGE (
o
C)
PACKAGE
DESIGNATOR
5962F9863201VCC
ACS109DMSR-03
-55 to 125
16 Ld SBDIP
CDIP2-T16
ACS109D/SAMPLE-03
ACS109D/SAMPLE-03
25
16 Ld SBDIP
CDIP2-T16
5962F9863201VXC
ACS109KMSR-03
-55 to 125
16 Ld Flatpack
CDFP4-F16
ACS109K/SAMPLE-03
ACS109K/SAMPLE-03
25
16 Ld Flatpack
CDFP4-F16
5962F9863201V9A
ACS109HMSR-03
25
Die
NA
Pinouts
ACS109MS
(SBDIP)
TOP VIEW
ACS109MS
(FLATPACK)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
1R
1J
1K
1CP
1S
1Q
GND
1Q
V
CC
2J
2K
2CP
2S
2Q
2Q
2R
1R
1J
1K
1CP
1S
1Q
1Q
GND
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
V
CC
2R
2J
2K
2CP
2S
2Q
2Q
Data Sheet
July 1999
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACS109K | Radiation Hardened Dual J-K Flip-Flop with Set and Reset |
| ACS10D | Radiation Hardened Triple Three-Input NAND Gate |
| ACS10DMSR | Radiation Hardened Triple Three-Input NAND Gate |
| ACS10K | Radiation Hardened Triple Three-Input NAND Gate |
| ACS10KMSR | Radiation Hardened Triple Three-Input NAND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACS109K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual J-K Flip-Flop with Set and Reset |
| ACS109MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual J-K Flip-Flop with Set and Reset |
| ACS10D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple Three-Input NAND Gate |
| ACS10DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple Three-Input NAND Gate |
| ACS10DMSR-02 | 制造商:Intersil Corporation 功能描述:RAD HARD TRIPLE 3-INPUT NAND GATE,DIP,300KRAD,CMOS,CLS V - Rail/Tube |
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