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參數(shù)資料
| 型號(hào)： | ACS02D |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened Quad 2-Input NOR Gate |
| 中文描述： | 輻射加固四2輸入或非門 |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 50K |
| 代理商： | ACS02D |
1
ACS02MS
Radiation Hardened Quad 2-Input NOR Gate
The Radiation Hardened ACS02MS is a Quad 2-Input NOR
Gate. For each gate, a HIGH level on either A or B input
results in a LOW level on the Y output. A LOW level on both
the A and B inputs results in a HIGH level on the Y output.
All inputs are buffered and the outputs are designed for
balanced propagation delay and transition times.
The ACS02MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS02MS are
contained in SMD 5962-98601. A “hot-link” is provided
on our homepage with instructions for downloading.
www.intersil.com/data/sm/index.asp
Features
QML Qualified Per MIL-PRF-38535 Requirements
1.25 Micron Radiation Hardened SOS CMOS
Radiation Environment
- Latch-Up Free Under Any Conditions
- Total Dose. . . . . . . . . . . . . . . . . . . . . . . 3 x 10
5
RAD(Si)
- SEU Immunity. . . . . . . . . . . . .<1 x 10
-10
Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm
2
)
Input Logic Levels. . . . V
IL
= (0.3)(V
CC
), V
IH
= (0.7)(V
CC
)
Output Current . . . . . . . . . . . . . . . . . . . . . . . .
±
8mA (Min)
Quiescent Supply Current . . . . . . . . . . . . . . 100
μ
A (Max)
Propagation Delay . . . . . . . . . . . . . . . . . . . . . .12ns (Max)
Applications
High Speed Control Circuits
Sensor Monitoring
Low Power Designs
Ordering Information
ORDERING NUMBER
INTERNAL MARKETING
NUMBER
TEMP. RANGE (
o
C)
PACKAGE
DESIGNATOR
5962F9860101VCC
ACS02DMSR-03
-55 to 125
14 Ld SBDIP
CDIP2-T14
ACS02D/SAMPLE-03
ACS02D/SAMPLE-03
25
14 Ld SBDIP
CDIP2-T14
5962F9860101VXC
ACS02KMSR-03
-55 to 125
14 Ld Flatpack
CDFP4-F14
ACS02K/SAMPLE-03
ACS02K/SAMPLE-03
25
14 Ld Flatpack
CDFP4-F14
5962F9860101V9A
ACS02HMSR-03
25
Die
N/A
Pinouts
ACS02MS
(SBDIP)
TOP VIEW
ACS02MS
(FLATPACK)
TOP VIEW
1Y
A1
B1
Y2
A2
B2
GND
V
CC
Y4
B4
A4
Y3
B3
A3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1
1Y
A1
B1
Y2
A2
B2
GND
V
CC
Y4
B4
A4
Y3
B3
A3
Data Sheet
November 1998
File Number
4540
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
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