參數(shù)資料
型號(hào)： ACPL-W481-560E
元件分類： 光電耦合器
英文描述： 1 CHANNEL LOGIC OUTPUT OPTOCOUPLER
封裝： ROHS COMPLIANT, SOP-6
文件頁數(shù)： 1/9頁
文件大?。?/td> 145K
代理商： ACPL-W481-560E
ACPL-P481/W481
Inverted Logic, High CMR Optocoupler for Intelligent
Power Modules and IGBT/MOSFET Gate Drive
Data Sheet
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Features
x Inverted output type (totem pole output)
x Performance Specified for Common IPM Applications
Over Industrial Temperature Range.
x Short Maximum Propagation Delays
x Minimized Pulse Width Distortion (PWD)
x Very High Common Mode Rejection (CMR)
x Hysteresis
x Available in Stretched SO-6 Package.
x Package Clearance/Creepage at 8 mm (ACPL-W481)
x Safety Approval: (pending)
– UL Recognized with 3750 Vrms for 1 minute per
UL1577.
– CSA Approved.
– IEC/EN/DIN EN 60747-5-5 Approved with VIORM =
891 Vpeak for ACPL-P481 and VIORM = 1140 Vpeak for
ACPL-W481, under option 060.
Specifications
x Wide Operating Temperature Range: –40°C to 100°C.
x Maximum Propagation Delay tPHL / tPLH = 350 ns
x Maximum Pulse Width Distortion (PWD) = 250 ns.
x Propagation Delay Difference: Min. –100 ns, Max. 250 ns
x Wide Operating VCC Range: 4.5 V to 20 V
x 20 kV/Ps Minimum Common Mode Rejection (CMR) at
VCM = 1000 V.
Truth Table (Positive Logic)
LED
VO
ON
LOW
OFF
HIGH
Description
The high-speed ACPL-P481/W481 optocoupler contains
a GaAsP LED, photo detector and a Schmitt trigger that
eliminates the need for external waveform conditioning
circuits.
The totem pole output eliminates the need for a pull-up
resistor. An Intelligent Power Module, Power MOSFET or
IGBT can be driven directly.
Propagation delay difference between devices has been
minimized to maximize inverter efficiency through
reduced switching dead time.
Applications
x IPM Interface Isolation
x Isolated IGBT/MOSFET Gate Drive
x AC and Brushless DC Motor Drives
x Industrial Inverters
x General Digital Isolation
Functional Diagram
Note: A 0.1
PF bypass capacitor must be connected between pins 4 and 6.
Ground
VCC
Anode
N.C.
Cathode
VO
6
1
5
2
4
3
SHIELD
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