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參數(shù)資料
| 型號(hào)： | ACH16823DL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Circular Connector; MIL SPEC:MIL-DTL-38999 Series II; Body Material:Metal; Series:JT; No. of Contacts:13; Connector Shell Size:10; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight RoHS Compliant: No |
| 中文描述： | ALVC/VCX/A SERIES, DUAL 9-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | PLASTIC, SOT-371, SSOP2-56 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 103K |
| 代理商： | ACH16823DL |
Philips Semiconductors
Product specification
74ALVCH16823
18-bit D-type flip-flop (3-State)
2
1998 Jul 29
853–2100 19800
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive
±
24 mA at 3.0 V
Multibyte
flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins to minimize noise and
ground bounce
All data inputs have bus hold
Output drive capability 50
transmission lines @ 85
°
C
DESCRIPTION
The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring
separate D-type inputs for each flip-flop and 3-state outputs for bus
oriented applications. Incorporates bushold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs. The74ALVCH16823 consists of two sections of nine
edge-triggered flip-flops. A clock (CP) input, an output-enable (OE)
input, a Master reset (MR) input and a clock-enable( CE) input are
provided for each total 9-bit section.
With the clock-enable (CE) input LOW, the D-type flip-flops will store
the state of their individual D-inputs that meet the set-up and hold
time requirements on the LOW-to-HIGH CP transition. Taking CE
HIGH disables the clock buffer, thus latching the outputs. Taking the
Master reset (MR) input LOW causes all the Q outputs to go LOW
independently of the clock.
When OE is LOW, the contents of the flip-flops are available at the
outputs. When the OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of flip-flops.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
CP to Qn
V
CC
= 2.5V, CL = 30pF
V
CC
= 3.3V, CL = 50pF
V
CC
= 2.5V, CL = 30pF
V
CC
= 3.3V, CL = 50pF
2.1
2.1
ns
F
max
Maximum clock frequency
300
350
MHz
C
I
Input capacitance
5.0
pF
C
PD
Power dissipation capacitance per latch
V = GND to V
CC1
Outputs enabled
16
pF
Outputs disabled
10
NOTES:
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type II
-40
°
C to +85
°
C
74ALVCH16823 DL
ACH16823 DL
SOT371-1
56-Pin Plastic TSSOP Type II
-40
°
C to +85
°
C
74ALVCH16823 DGG
ACH16823 DGG
SOT364-1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACH16825DGG | Circular Connector; MIL SPEC:MIL-DTL-38999 Series II; Body Material:Metal; Series:JT; No. of Contacts:5; Connector Shell Size:10; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight RoHS Compliant: No |
| ACH16827DGG | JT 5C 5#20 SKT PLUG |
| ACH16841DGG | Circular Connector; MIL SPEC:MIL-DTL-38999 Series II; Body Material:Metal; Series:JT; No. of Contacts:5; Connector Shell Size:10; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight RoHS Compliant: No |
| ACH16843DGG | JT 6C 6#20 PIN PLUG |
| ACH16952DGG | JT 6C 6#20 SKT WALL RECP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACH16825DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit buffer/driver 3-State |
| ACH16827DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:20-bit buffer/line driver, non-inverting 3-State |
| ACH16841DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:20-bit bus interface D-type latch 3-State |
| ACH16843DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit bus-interface D-type latch 3-State |
| ACH16952DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16-bit registered transceiver 3-State |
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