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參數(shù)資料
| 型號(hào)： | ACH16374DL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | JT 13C 13#22M SKT PLUG |
| 中文描述： | ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 96K |
| 代理商： | ACH16374DL |
Philips Semiconductors
Product specification
74ALVCH16374
16-bit edge-triggered D-type flip-flop (3-State)
2
1998 Jun 18
853-2073 19604
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple V
CC
and ground pins for minimum noise
and ground bounce
Direct interface with TTL levels
All data inputs have bushold
Output drive capability 50
transmission lines @ 85
°
C
Current drive
±
24 mA at 3.0 V
DESCRIPTION
The 74ALVCH16374 is a 16-bit edge-triggered flip-flop featuring
separate D-type inputs for each flip-flop and 3-State outputs for bus
oriented applications. Incorporates bus hold data inputs which
eliminate the need for external pull-up or pull-down resistors to hold
unused inputs. The 74ALVCH16374 consists of 2 sections of eight
edge-triggered flip-flops. A clock (CP) input and an output enable
(OE) are provided per 8-bit section.
The flip-flops will store the state of their individual D-inputs that meet
the set-up and hold time requirements on the LOW-to-HIGH CP
transition.
When OE is LOW, the contents of the flip-flops are available at the
outputs. When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the state of the
flip-flops.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
1Q4
2Q2
2Q3
V
CC
2Q4
2Q5
2D5
2D4
V
CC
2D3
2D2
GND
2D1
2D0
1D7
1D6
GND
1D5
1D4
V
CC
1D3
1D2
GND
1D1
1D0
1CP
21
22
23
24
25
26
27
28
GND
2Q6
2Q7
2OE
2CP
2D7
2D6
GND
SW00074
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
PLH
/t
Propagation delay
CP to Qn
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
V
CC
= 2.5V
V
CC
= 3.3V
2.3
ns
y
2.4
f
MAX
Maximum clock frequency
300
MHz
350
MHz
C
I
Input capacitance
5.0
pF
C
PD
Power dissipation capacitance per flip flop
Power dissipation capacitance per flip-flop
V = GND to V
CC1
Outputs enabled
16
pF
Outputs disabled
10
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V; (C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
48-Pin Plastic SSOP Type III
–40
°
C to +85
°
C
74ALVCH16374 DL
ACH16374 DL
SOT370-1
48-Pin Plastic TSSOP Type II
–40
°
C to +85
°
C
74ALVCH16374 DGG
ACH16374 DGG
SOT362-1
相關(guān)PDF資料 |
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| ACH16540DGG | JT 13C 13#22D PIN WALL RECP |
| ACH16540DL | 2.5V/3.3V 16-bit buffer/line driver, inverting, 5V input tolerant 3-State |
| ACH16543DGG | JT 13C 13#22D PIN PLUG |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACH16540DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.5V/3.3V 16-bit buffer/line driver, inverting, 5V input tolerant 3-State |
| ACH16540DL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.5V/3.3V 16-bit buffer/line driver, inverting, 5V input tolerant 3-State |
| ACH16543DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16-bit D-type registered transceiver; 3-state |
| ACH16646DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16-bit bus transceiver/register 3-State |
| ACH16652DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16-bit transceiver/register with dual enable; 3-state |
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