參數(shù)資料
型號(hào): ACF2101BU
英文描述: Low Noise, Dual SWITCHED INTEGRATOR
中文描述: 低噪聲,雙交換式積分器
文件頁數(shù): 7/14頁
文件大?。?/td> 192K
代理商: ACF2101BU
ACF2101
7
APPLICATIONS INFORMATION
BASIC CIRCUIT CONNECTION
Basic Layout
As with any precision circuit, careful layout will ensure best
performance. Make short, direct interconnections and avoid
stray wiring capacitance—especially at the analog and
digital input pins.
Figures 1a and 1b illustrate the basic connections needed for
operation. Figures 1c and 1d illustrate the addition of
external integration capacitors and input guards.
Leakage currents between printed circuit board traces can
easily exceed the input bias current of the ACF2101. A
circuit board “guard” pattern reduces leakage effects by
surrounding critical high impedance input circuitry with a
low impedance circuit connection at the same potential.
Leakage will flow harmlessly to the low impedance node.
Figure 2a and 2b show printed circuit patterns that can be
used to guard critical pins. Note that traces leading to these
pins should also be guarded.
Improper handling or cleaning may increase droop. Con-
tamination from handling parts and circuit boards can be
removed with cleaning solvents and de-ionized water.
Pinout
The pinout for the DIP and SOIC package of the ACF2101 is
different. The pinouts for the different packages are shown in
several figures in this data sheet.
Power Supplies
The ACF2101 can operate from supplies that range from
+4.5V and –10V to
±
18V. Since the output voltage
integrates negatively from ground, a positive supply of +5V
is sufficient to attain specified performance. Using +5V and
–15V power supplies reduces power dissipation by one-half
of that at
±
15V.
Power supply connections should be bypassed with good
high-frequency capacitors, such as 1
μ
F solid tantalum
capacitors, positioned close to the power supply pins.
FIGURE 1a. Basic Circuit Connections,
SOIC package
.
FIGURE 1b. Basic Circuit Connections,
DIP
.
Top View
ACF2101BU
Top View
ACF2101BP
Sw In B
In B
Cap B
Com B
Gnd B
Out B
V–
Sw In A
In A
Cap A
Com A
Gnd A
Out A
V+
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1
μ
F
V–
1
μ
F
V+
These points must be connected to a
common ground point or a ground plane.
Input
Input
+
+
V
OUT
V
OUT
SOIC
Out A
Gnd A
Com A
Cap A
In A
Sw In A
Sw In B
In B
Cap B
Com B
Gnd B
Out B
V+
V–
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
These points must be connected to a
c
Input
V
OUT
V+
DIP
Input
V
OUT
V–
1
μ
F
1
μ
F
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