參數(shù)資料
型號(hào): ACD2203S8GP1
廠(chǎng)商: ANADIGICS INC
元件分類(lèi): 衰減器
英文描述: JT 55C 55#22D SKT PLUG
中文描述: RF/MICROWAVE DOWN CONVERTER
封裝: S8, MO-137AF, SSOP-28
文件頁(yè)數(shù): 14/24頁(yè)
文件大小: 618K
代理商: ACD2203S8GP1
14
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
ACD2203
Programmable Modes
Each register contains bits set aside for programming
different modes of operation in the synthesizers. Bit
D1 in each reference divider register controls the phase
detector polarity. Table 14 shows how this bit controls
the polarity, and the correct setting is determined by
using Table 15 and Figure 22.
Table 15: Phase Detector Polarity Selection
D
1
Y
T
R
A
L
O
P
O
E
C
T
V
C
S
C
I
T
S
I
R
A
R
A
H
C
0
e
v
g
e
N
)
e
v
c
1
e
v
o
P
)
e
v
c
Figure 22: VCO Characteristics
(1)
(2)
VCO INPUT VOLTAGE
VCO OUTPUT
FREQUENCY
Bit C1 in each main divider register sets the
prescalar mode. Table 16 indicates the appropriate
settings. (Currently, there is only one prescalar
mode available for use.)
Table 16: Prescalar Mode
C
1
E
D
O
M
R
A
L
A
C
S
E
R
P
0
5
6
6
1
)
s
u
e
d
e
v
s
e
Table 14: Phase Detector Polarity Bit
S
2
S
1
D
1
0
0
y
P
r
e
D
e
s
a
h
P
2
L
L
P
1
0
y
P
r
e
D
e
s
a
h
P
1
L
L
P
Table 13: Main Divider A Counter Bits
Notes:
B > A, A < P
A
F
E
O
T
E
N
U
U
L
O
A
C
V
R
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
-
-
-
-
-
-
-
-
7
2
1
1
1
1
1
1
1
1
Bit C2 in the main divider registers, bits D2 through
D5 in the reference divider registers, and bits X1
and X2 in all registers are reserved for future use,
and have no current function. They can be set either
high or low without affecting synthesizer
performance.
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