參數(shù)資料
型號: AC164140
廠商: Microchip Technology
文件頁數(shù): 12/14頁
文件大?。?/td> 0K
描述: KIT MCP79410 RTCC DAUGHTER BOARD
標準包裝: 1
系列: PICtail™ Plus
主要目的: 計時,實時時鐘(RTC)
已用 IC / 零件: MCP79410
主要屬性: For Use With Explorer 16,PICDEM PIC18 Explorer,XLP DEV Board,PICkit Serial Analyzer
已供物品: 板,電池,文檔
相關(guān)產(chǎn)品: MCP79410T-I/SN-ND - IC RTC/CALENDAR EEPROM 8SOIC
MCP79410T-I/MS-ND - IC RTC/CALENDAR EEPROM 8MSOP
MCP79410T-I/ST-ND - IC RTC/CALENDAR EEPROM 8TSSOP
MCP79410T-I/MNYDKR-ND - IC RTC/CALENDAR EEPROM 8TDFN
MCP79410T-I/MNYCT-ND - IC RTC/CALENDAR EEPROM 8TDFN
MCP79410T-I/MNYTR-ND - IC RTC/CALENDAR EEPROM 8TDFN
MCP79410-I/ST-ND - IC RTC ALARM NVSRAM 8TSSOP
MCP79410-I/SN-ND - IC RTC ALARM NVSRAM 8SOIC
MCP79410-I/MS-ND - IC RTC ALARM NVSRAM 8MSOP
SY87702L
7
Micrel, Inc.
M9999-072706
hbwhelp@micrel.com or (408) 955-1690
VCOSEL1
VCOSEL2
FREQSEL1
FREQSEL2
FREQSEL3
Range (Mbps)
00000
2488 (OC48)
00001
1244
00010
622 (OC12)
00100
311
00110
155 (OC3)
01000
1800–2500
01001
900–1250(1)
10000
1250–1800
11000
650–1300(2)
11001
325–650(3)
11010
163–325
11011
109–216
11100
82–162
11101
55–108
11110
41–81
11111
28–54
Table 4.(4)
DESCRIPTION
General
The SY87702L is a complete clock and data recovery
circuit, capable of dealing with NRZ data rates from 28Mbps
through to 2.5Gbps. A reference PLL is used as a frequency
synthesizer, both to multiply a clock to the desired transmit
rate, and to train the recovery PLL in preparation for actual
data recovery.
VCO Selection
SY87702L has four complete VCO circuits. Depending
of the application and the frequency range, any one of
these four perform data recovery.
As indicated by the VCO selection table, there are three
general purpose VCOs, covering one of three frequency
ranges. However, to extend the range of the device, the
output of the VCO may be divided down.
In the case of the two highest frequency VCO, this divisor
is always set to 1. For the lowest frequency VCO, the
FREQSEL pins select which divisor, and hence, which range
of frequencies the VCO will work over.
In addition, for SONET/SDH applications, there is a narrow
band, extremely low jitter PLL. It also uses the FREQSEL
divisor to choose the correct SONET/SDH frequency.
The various combinations of FREQSEL and VCOSEL
are not arbitrary, but are limited to the subset shown in
Table 4, where the range column indicates frequency in
Mbps.
NOTES:
1. Suggested range for Fibre Channel applications.
2. REFCLK multiplier of 2 is not allowed in this range.
3. REFCLK multiplier of 1 is not allowed in this range.
4. Combinations of VCOSEL and FREQSEL other then those in this table result in undefined behavior, and should not be
used.
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