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參數(shù)資料
| 型號： | ABT574A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS |
| 中文描述： | 八路邊沿觸發(fā)的D型倒裝3觸發(fā)器態(tài)輸出 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大小： | 287K |
| 代理商： | ABT574A |
SN54ABT574, SN74ABT574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS191E
–
JANUARY 1991
–
REVISED NOVEMBER 2002
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500
500
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V
1.5 V
3 V
0 V
3 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
1.5 V
1.5 V
Input
1.5 V
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH
–
0.3 V
≈
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST
S1
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
, tr
≤
2.5 ns, tf
≤
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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