參數(shù)資料
型號(hào): AB28F200BR
廠商: Intel Corp.
英文描述: 5 V Automotive Boot Block Flash Memory(5V自引導(dǎo)塊閃速存儲(chǔ)器)
中文描述: 5伏汽車啟動(dòng)塊閃存(5V的自引導(dǎo)塊閃速存儲(chǔ)器)
文件頁數(shù): 8/40頁
文件大?。?/td> 257K
代理商: AB28F200BR
AB28F200BR, AB28F400BR
E
8
ADVANCE INFORMATION
Table 2. Pin Descriptions
(Continued)
Symbol
Type
Name and Function
WP#
INPUT
WRITE PROTECT:
Provides a method for unlocking the boot block with a logic
level signal in a system without a 12 V supply.
When WP# is at logic low, the boot block is locked
, preventing program and
erase operations to the boot block. If a program or erase operation is attempted
on the boot block when WP# is low, the corresponding status bit (bit 4 for
program, bit 5 for erase) will be set in the status register to indicate the operation
failed.
When WP# is at logic high, the boot block is unlocked
and can be
programmed or erased.
NOTE:
This feature is overridden and the boot block unlocked when RP# is at
V
. This pin can not be left floating. Because the 8-Mbit 44-PSOP package does
not have enough pins, it does not include this pin and thus 12 V on RP# is
required to unlock the boot block. See Section 3.3 for details on write protection.
BYTE#
INPUT
BYTE# ENABLE:
Configures whether the device operates in byte-wide mode (x8)
or word-wide mode (x16). This pin must be set at power-up or return from deep
power-down and not changed during device operation. BYTE# pin must be
controlled at CMOS levels to meet the CMOS current specification in standby
mode.
When BYTE# is at logic low, the byte-wide mode is enabled
, where data is
read and programmed on DQ
0
–DQ
7
and DQ
15
/A
–1
becomes the lowest order
address that decodes between the upper and lower byte. DQ
8
–DQ
14
are tri-stated
during the byte-wide mode.
When BYTE# is at logic high, the word-wide mode is enabled
, where data is
read and programmed on DQ
0
–DQ
15
.
V
CC
DEVICE POWER SUPPLY:
5.0 V
±
10%
V
PP
PROGRAM/ERASE POWER SUPPLY:
For erasing memory array blocks or
programming data in each block, a voltage either of 5 V
±
10% or 12 V
±
5% must
be applied to this pin. When V
PP
< V
PPLK
all blocks are locked and protected
against Program and Erase commands.
GND
GROUND:
For all internal circuitry.
NC
NO CONNECT:
Pin may be driven or left floating.
相關(guān)PDF資料
PDF描述
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參數(shù)描述
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