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參數(shù)資料
| 型號(hào)： | AAT3151 |
| 廠商： | Advanced Analog Technology,lnc. |
| 英文描述： | High Efficiency 1X/1.5X/2X Charge Pump For White LED Applications |
| 中文描述： | 高效率1x/1.5x/2x電荷泵白光LED應(yīng)用 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 431K |
| 代理商： | AAT3151 |
AAT3151
High Efficiency 1X/1.5X/2X Charge Pump
For White LED Applications
4
3151.2007.03.1.10
Electrical Characteristics
1
C
IN
= C
OUT
= C
1
= C
2
= 1.0μF; T
A
= -40°C to +85°C, unless otherwise noted.
Typical values are T
A
= 25°C, V
IN
= 3.5V.
Symbol
Input Power Supply
V
IN
Description
Conditions
Min
Typ
Max
Units
Operation Range
2.7
5.5
1
V
1X Mode, 3.0
≤
V
IN
≤
5.5, Active,
No Load Current
1.5X Mode, 3.0
≤
V
IN
≤
5.5, Active,
No Load Current
2X Mode, 3.0
≤
V
IN
≤
5.5, Active,
No Load Current
50μA Setting, 1X Mode
EN/SET = 0
I
SET
= 30mA, T
A
= 25°C
0.3
1
3
mA
I
CC
Operating Current
2.0
3.7
50
μA
μA
mA
I
SHDN
I
DX
Shutdown Current
I
SINK
Current Accuracy
2
Current Matching Between Any
Two Current Sink Inputs
3, 4
1X to 1.5X or 1.5X to 2X Transition
Threshold at Any I
SINK
Pin
Charge Pump Section
T
SS
Soft-Start Time
F
CLK
Clock Frequency
EN/SET
V
IL
Enable Threshold Low
V
IH
Enable Threshold High
T
EN/SET LO
EN/SET Low Time
T
EN/SET_HI_MIN
Minimum EN/SET High Time
T
EN/SET_HI_MAX
Maximum EN/SET High Time
T
OFF
EN/SET Off Timeout
5
T
LAT
EN/SET Latch Timeout
6
I
EN/SET
EN/SET Input Leakage
1
33
27
30
I
(D-Match)
V
F
:D1:D4 = 3.6V
0.5
%
V
TH
I
SET
= 20mA
150
mV
100
1000
μs
kHz
V
IN
= 2.7V
V
IN
= 5.5V
0.4
V
V
μs
ns
μs
μs
μs
μA
1.4
0.3
75
50
75
500
500
1
-1
1. The AAT3151 is guaranteed to meet performance specifications over the -40°C to +85°C operating temperature range and is assured
by design, characterization, and correlation with statistical process controls.
2. Determined by the average of all active channels.
3. Current matching is defined as the deviation of any sink current at I
OUT
= 20mA and 2mA.
4. Specification applies only to the tri-mode charge pump.
5. The EN/SET pin must remain logic low (less than V
IL
) for the duration of longer than 500μs to guarantee the off timeout.
6. The EN/SET pin must remain logic high (greater than V
IH
) for the duration of longer than 500μs to guarantee the latch timeout.
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