參數(shù)資料
型號: AAT3114AISN-20-T1
廠商: Advanced Analog Technology,lnc.
英文描述: High Efficiency 1.5X Fractional Charge Pumps For White LED Applications
中文描述: 高效率1.5倍分?jǐn)?shù)電荷泵為白光LED應(yīng)用
文件頁數(shù): 8/15頁
文件大?。?/td> 331K
代理商: AAT3114AISN-20-T1
AAT3113, AAT3114/14A
High Efficiency 1.5X Fractional Charge
Pumps For White LED Applications
8
3113.2006.07.1.9
Functional Block Diagram
Voltage
Reference
Soft Start
600kHz
Oscillator
1.5X
Charge
Pump
S
2
Cwire
Interface
32x8 bit
ROM
Current
Mode
DAC
8
5
VIN
C1+
C1-
C2+
C2-
OUT
D1
D2
D3
D4
D5*
D6*
GND
* AAT3114/14A only
EN/SET
Functional Description
The AAT3113 and AAT3114/14A devices are high
efficiency 1.5X fractional charge pumps intended
for white LED backlight applications. The fraction-
al charge pump consists of a linear regulator fol-
lowed by a 1.5X charge pump. The AAT3113 and
AAT3114/14A require only four external compo-
nents: two 1μF ceramic capacitors for the charge
pump flying capacitors (C1 and C2), one 1μF
ceramic capacitor for C
IN
, and one 0.33μF to 1μF
ceramic capacitor for C
OUT
. The charge pump out-
put is converted into four or six constant current
outputs (D1 to D4 or D6) to drive four or six indi-
vidual LEDs with a maximum of 20mA each. The
current source output magnitude is controlled by
the EN/SET serial data S
2
Cwire interface. The
interface records rising edges of the EN/SET pin
and decodes them into 32 individual current level
settings each 1dB apart (see Table 1, Current
Level Settings). Code 32 is full scale, and Code 1
is full scale attenuated by 31dB. The modulo 32
interface wraps states back to state 1 after the
32nd clock. With each EN/SET pulse, the output
current increases by 1dB. To decrease the output
current by 1dB, 31 EN/SET clock pulses are
required. The counter can be clocked at speeds up
to 1MHz, so intermediate states are not visible.
The first rising edge of EN/SET enables the IC and
initially sets the output LED current to -31dB, the
lowest setting equal to 525μA. Once the final clock
cycle is input for the desired brightness level, the
EN/SET pin is held high to maintain the device out-
put current at the programmed level. The device is
disabled 500μs after the EN/SET pin transitions to
a logic low state.
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