參數(shù)資料
型號(hào): AAT2554
廠(chǎng)商: Advanced Analog Technology,lnc.
英文描述: Total Power Solution for Portable Applications
中文描述: 總功率便攜式應(yīng)用解決方案
文件頁(yè)數(shù): 26/33頁(yè)
文件大?。?/td> 877K
代理商: AAT2554
AAT2554
Total Power Solution for Portable Applications
26
2554.2007.01.1.2
Figure 5: AAT2554 Evaluation Board Schematic.
1
2
3
JP2
ENA
L1
ADP
1
2
3
JP1
EN_BAT
D1
VINB
VOUTB
1
2
VBAT
VOUTA
GND
1
2
3
JP3
ENB
C7
2.2μF
C3
4.7μF
C1
4.7μF
VOUTA
VOUTB
FB
ENB
EN_BAT
ADP
VINA
ADP
R7
100K
R6
100K
R5
100K
R3
59K
R2
118K
R1
8.06K
C8
100pF
C4
4.7μF
C6
2.2μF
C5
2.2μF
R4
1K
GND
12
LX
15
VINB
16
BAT
8
STAT
9
OUTA
5
FB
1
GND
14
ADP
11
VINA
4
ENB
3
ENA
13
EN_BAT
6
ISET
7
GND
10
GND
2
AAT2554
U1
VINB
VINB
ENA
C8 optional for
enhanced step-
down converter
transient
response
Printed Circuit Board Layout
Considerations
For the best results, it is recommended to physi-
cally place the battery pack as close as possible to
the AAT2554 BAT pin. To minimize voltage drops
on the PCB, keep the high current carrying traces
adequately wide. Refer to the AAT2554 evaluation
board for a good layout example (see Figures 6
and 7). The following guidelines should be used to
help ensure a proper layout.
1. The input capacitors (C1, C3, C7) should con-
nect as closely as possible to ADP (Pin 11),
VINA (Pin 4), and VINB (Pin 16).
2. C4 and L1 should be connected as closely as
possible. The connection of L1 to the LX pin
should be as short as possible. Do not make the
node small by using narrow trace. The trace
should be kept wide, direct, and short.
3. The feedback pin (Pin 1) should be separate
from any power trace and connect as closely as
possible to the load point. Sensing along a high-
current load trace will degrade DC load regula-
tion. Feedback resistors should be placed as
closely as possible to the FB pin (Pin 1) to mini-
mize the length of the high impedance feedback
trace. If possible, they should also be placed
away from the LX (switching node) and inductor
to improve noise immunity.
4. The resistance of the trace from the load return
GND (Pins 2, 10, 12, and 14) should be kept to
a minimum. This will help to minimize any error
in DC regulation due to differences in the poten-
tial of the internal signal ground and the power
ground.
5. A high density, small footprint layout can be
achieved using an inexpensive, miniature, non-
shielded, high DCR inductor.
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