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參數(shù)資料
| 型號(hào)： | AAT1232ITP-T1 |
| 廠商： | Advanced Analog Technology,lnc. |
| 英文描述： | 24V 100mA Step-Up Converter |
| 中文描述： | 24V的100mA的升壓轉(zhuǎn)換器 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 416K |
| 代理商： | AAT1232ITP-T1 |
AAT1232
24V 100mA Step-Up Converter
14
1232.2006.12.1.3
S
2
Cwire Output Voltage Programming
The AAT1232 is programmed through the S
2
Cwire
interface according to Table 2. The rising clock
edges received through the EN/SET pin determine
the feedback reference and output voltage set-
point. Upon power up with the SEL pin low and
prior to S
2
Cwire programming, the default feed-
back reference voltage is set to 0.6V.
PCB Layout Guidelines
Boost converter performance can be adversely
affected by poor layout. Possible impact includes
high input and output voltage ripple, poor EMI per-
formance, and reduced operating efficiency. Every
attempt should be made to optimize the layout in
order to minimize parasitic PCB effects (stray
resistance, capacitance, inductance) and EMI cou-
pling from the high frequency SW node.
A suggested PCB layout for the AAT1232 boost
converter is shown in Figures 4 and 5. The follow-
ing PCB layout guidelines should be considered:
1.
Minimize the distance from capacitor C1 and
C2 negative terminal to the PGND pins. This is
especially true with output capacitor C2, which
conducts high ripple current from the output
diode back to the PGND pins.
Place the feedback resistors close to the output
terminals. Route the output pin directly to resis-
tor R1 to maintain good output regulation. R3
should be routed close to the output GND pin.
Minimize the distance between L1 to D1 and
switching pin SW; minimize the size of the PCB
area connected to the SW pin.
Maintain a ground plane and connect to the IC
RTN pin(s) as well as the GND terminals of C1
and C2.
Consider additional PCB area on D1 cathode
to maximize heatsinking capability. This may
be necessary when using a diode with a high
thermal resistance.
When using the TDFN34-16 package, connect
paddle to SW pin or leave floating. Do not con-
nect to RTN/GND conductors.
2.
3.
4.
5.
6.
Figure 4: AAT1232 Evaluation Board
Top Side.
Figure 5: AAT1232 Evaluation Board
Bottom Side.
Figure 3: S
2
Cwire Timing Diagram to Program the Output Voltage.
1
EN/SET
2
n-1
n
≤
16
Data Reg
0
n-1
0
T
HI
T
LO
T
LAT
T
OFF
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